Patents by Inventor Jiye Yang

Jiye Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230112037
    Abstract: The present disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate doped with a first ion, a deep trench structure disposed in the substrate, a barrier doped region disposed on a top of the substrate and the deep trench structure, a first epitaxial layer disposed on the barrier doped region, a body region disposed in the first epitaxial layer, a source region disposed in the body region, a gate structure disposed in the first epitaxial layer, and a collector region disposed at a bottom of the substrate. By means of the semiconductor structure, performance of an insulated gate bipolar transistor can be improved.
    Type: Application
    Filed: August 11, 2022
    Publication date: April 13, 2023
    Applicant: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Jia PAN, Peng SUN, Yiping YAO, Jiye YANG, Junjun XING, Chong CHEN, Xuan HUANG, Tongbo ZHANG
  • Publication number: 20230101771
    Abstract: An IGBT device and a method for manufacturing it, the device includes a super junction structure that has several N-type pillars and P-type pillars arranged alternately; a cell unit that is located in an N-type epitaxial layer, and the N-type epitaxial layer is located above the N-type substrate; each cell unit includes a trench gate, a P-type body region, and a source region; an N-type carrier injection layer, the N-type carrier injection layer is located in the N-type epitaxial layer, and the N-type carrier injection layer is spaced apart from the N-type substrate by the N-type epitaxial layer; the bottom of the P-type body region is located in the N-type carrier injection layer; and a collector region that is located at the bottom of the N-type substrate.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 30, 2023
    Inventors: Jia PAN, Tongbo ZHANG, Yiping YAO, Jiye YANG, Junjun XING, Chong CHEN, Xuan HUANG, Peng SUN
  • Publication number: 20230031623
    Abstract: A corrugated shadow mask for patterned vapor deposition includes a corrugated membrane under tensile stress with a plurality of through-apertures forming an aperture array through which a vaporized deposition material can pass. The through-apertures are at the apexes of the corrugation and project from the membrane surface surrounding the through-apertures. The shadow mask is particularly suited for forming pixel arrays for OLED displays without color mixing from adjacent pixels.
    Type: Application
    Filed: September 16, 2022
    Publication date: February 2, 2023
    Inventors: Shoucheng DONG, Jiye YANG, Ching Wan TANG
  • Patent number: 11374123
    Abstract: The present disclosure discloses a trench gate semiconductor device, wherein a trench gate includes a trench formed in a semiconductor substrate, and a gate oxide layer formed on a bottom surface and a side surface of the trench; the gate oxide layer is formed by stacking a first oxide layer and a second oxide layer; the first oxide layer is a furnace tube thermal oxide layer; the second oxide layer is a PECVD oxide layer; the gate oxide layer has a thermally densified structure processed by means of RTA. The present disclosure also discloses a method for manufacturing a trench gate semiconductor device. The present disclosure can increase BVGSS of the device, without affecting the threshold voltage of the device, with simple processes and low costs.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: June 28, 2022
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Jiye Yang, Longjie Zhao, Hao Li
  • Publication number: 20220167933
    Abstract: The present invention relates to an X-ray imaging apparatus which obtains an X-ray image of a subject placed between a generator and a detector by means of the rotation of the generator and the detector. The X-ray imaging apparatus comprises: the generator and the detector, which are disposed to face each other while having an object to be imaged therebetween, for irradiating and detecting an X-ray; a rotation drive unit for rotating the generator and the detector while having the object to be imaged therebetween; and a bed in which a first portion for supporting the object to be imaged is disposed between the generator and the detector. When the height of at least one from among the generator and the detector is T1, the height of the other is T2, and the height of the first portion is T3, said T1, T2, and T3 are T1>T3>T2.
    Type: Application
    Filed: March 9, 2020
    Publication date: June 2, 2022
    Applicants: Woorien Co., Ltd., VATECH EWOO Holdings Co., Ltd.
    Inventors: Byung Jun AHN, Jiye YANG, Jongbo YOON, Sung-il CHOI
  • Publication number: 20210376117
    Abstract: A method for manufacturing an IGBT device includes: forming a cell structure of the IGBT device in a substrate; forming front metal layers on the substrate; thinning the substrate; forming a collector region on the back of the substrate; forming back metal layers on the back of the substrate; and forming target metal on the front and back of the substrate via electroless plating processes.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 2, 2021
    Applicant: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Jia PAN, Jiye YANG, Junjun XING, Xuan HUANG
  • Patent number: 11139391
    Abstract: An IGBT device comprises a super-junction structure arranged in a drift region and formed by a plurality of N-type pillars and a plurality of P-type pillars which are alternately arrayed. Device cell structures of the IGBT device are formed in an N-type epitaxial layer at the tops of super-junction cells. Each device cell structure comprises a body region, a gate structure and an emitter region. N-type isolation layers having a doping concentration greater than that of the N-type epitaxial layer are formed between the bottom surfaces of the body regions and the top surfaces of the P-type pillars and are used for isolating the body regions from the P-type pillars. The super-junction structure and the N-type isolation layers can increase the current density of the device, decrease the on-state voltage drop of the device and reduce the turn-off loss of the device.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: October 5, 2021
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Jiye Yang, Junjun Xing, Jia Pan, Hao Li, Yi Lu, Longjie Zhao, Xukun Zhang, Xuan Huang, Chong Chen
  • Publication number: 20210119038
    Abstract: The present disclosure discloses a trench gate semiconductor device, wherein a trench gate includes a trench formed in a semiconductor substrate, and a gate oxide layer formed on a bottom surface and a side surface of the trench; the gate oxide layer is formed by stacking a first oxide layer and a second oxide layer; the first oxide layer is a furnace tube thermal oxide layer; the second oxide layer is a PECVD oxide layer; the gate oxide layer has a thermally densified structure processed by means of RTA. The present disclosure also discloses a method for manufacturing a trench gate semiconductor device. The present disclosure can increase BVGSS of the device, without affecting the threshold voltage of the device, with simple processes and low costs.
    Type: Application
    Filed: August 19, 2020
    Publication date: April 22, 2021
    Applicant: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Jiye YANG, Longjie ZHAO, Hao LI
  • Publication number: 20200219996
    Abstract: An IGBT device comprises a super-junction structure arranged in a drift region and formed by a plurality of N-type pillars and a plurality of P-type pillars which are alternately arrayed. Device cell structures of the IGBT device are formed in an N-type epitaxial layer at the tops of super-junction cells. Each device cell structure comprises a body region, a gate structure and a source region. N-type isolation layers having a doping concentration greater than that of the N-type epitaxial layer are formed between the bottom surfaces of the body regions and the top surfaces of the P-type pillars and are used for isolating the body regions from the P-type pillars. The super-junction structure and the N-type isolation layers can increase the current density of the device, decrease the on-state voltage drop of the device and reduce the turn-off loss of the device.
    Type: Application
    Filed: September 10, 2019
    Publication date: July 9, 2020
    Applicant: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION
    Inventors: Jiye YANG, Junjun XING, Jia PAN, Hao LI, Yi LU, Longjie ZHAO, Xukun ZHANG, Xuan HUANG, Chong CHEN
  • Patent number: 10680070
    Abstract: A trench gate manufacturing method includes the following steps: Step 1, forming a trench in the surface of a semiconductor substrate; Step 2, forming a first oxide layer; Step 3, selecting a coating according to the depth-to-width ratio of the trench and forming the coating completely filling the trench; Step 4, etching back the coating through a dry etching process; Step 5, conducting wet etching on the first oxide layer with the coating reserved at the bottom of the trench as a mask so as to form a gate bottom oxide; Step 6, removing the coating; and Step 7, growing a gate oxide. By adoption of the trench gate manufacturing method, a BTO can be realized at a low cost, and can be well-formed in trenches with smaller depth-to-width ratios and thus is suitable for forming BTOs in trenches with various depth-to-width ratios, thereby having a wider application range.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 9, 2020
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Jiye Yang, Hao Li, Lei Wang, Longjie Zhao, Xiaoxiang Sun
  • Publication number: 20190103466
    Abstract: A trench gate manufacturing method includes the following steps: Step 1, forming a trench in the surface of a semiconductor substrate; Step 2, forming a first oxide layer; Step 3, selecting a coating according to the depth-to-width ratio of the trench and forming the coating completely filling the trench; Step 4, etching back the coating through a dry etching process; Step 5, conducting wet etching on the first oxide layer with the coating reserved at the bottom of the trench as a mask so as to form a gate bottom oxide; Step 6, removing the coating; and Step 7, growing a gate oxide. By adoption of the trench gate manufacturing method, a BTO can be realized at a low cost, and can be well-formed in trenches with smaller depth-to-width ratios and thus is suitable for forming BTOs in trenches with various depth-to-width ratios, thereby having a wider application range.
    Type: Application
    Filed: September 26, 2018
    Publication date: April 4, 2019
    Applicant: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION
    Inventors: Jiye Yang, Hao Li, Lei Wang, Longjie Zhao, Xiaoxiang Sun