Patents by Inventor Ji Yong Woo

Ji Yong Woo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Two terminal switching device having bipolar switching property, method of fabricating the same, and resistive memory cross-point array having the same
    Patent number: 9178023
    Abstract: Provided are a two-terminal switching device having a bidirectional switching property, and a resistive memory cross-point array including the same. The two-terminal switching device includes a first electrode. A first tunneling barrier layer is disposed on the first electrode. An oxide semiconductor layer is disposed on the first tunneling barrier layer. A second tunneling barrier layer is disposed on the oxide semiconductor layer. A second electrode is disposed on the second tunneling barrier layer.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: November 3, 2015
    Assignee: POSTECH ACADEMY—INDUSTRY FOUNDATION
    Inventors: Hyunsang Hwang, Ji Yong Woo
  • MEMORY DEVICE AND MEMORY CELL ARRAY
    Publication number: 20150221701
    Abstract: A resistive memory device includes a stack of two layers of variable resistance material and top, middle, and bottom electrodes, the stack symmetrical in composition about the middle electrode.
    Type: Application
    Filed: December 1, 2014
    Publication date: August 6, 2015
    Applicant: Postech Academy-Industry Foundation
    Inventors: Min-kyu Yang, Young-bae Kim, Hyun-sang Hwang, Ji-yong Woo
  • TWO TERMINAL SWITCHING DEVICE HAVING BIPOLAR SWITCHING PROPERTY, METHOD OF FABRICATING THE SAME, AND RESISTIVE MEMORY CROSS-POINT ARRAY HAVING THE SAME
    Publication number: 20150048299
    Abstract: Provided are a two-terminal switching device having a bidirectional switching property, and a resistive memory cross-point array including the same. The two-terminal switching device includes a first electrode. A first tunneling barrier layer is disposed on the first electrode. An oxide semiconductor layer is disposed on the first tunneling barrier layer. A second tunneling barrier layer is disposed on the oxide semiconductor layer. A second electrode is disposed on the second tunneling barrier layer.
    Type: Application
    Filed: March 28, 2014
    Publication date: February 19, 2015
    Applicant: POSTECH ACADEMY - INDUSTRY FOUNDATION
    Inventors: Hyunsang Hwang, Ji Yong Woo