Abstract: Disclosed is a method for designing a semiconductor, which is performed by a computing device. The method may include acquiring connection relationship information between cells to be placed. The method may include generating two or more macro groups by grouping macro cells included in the connection relationship information. The method may include placing the two or more macro groups in a design area, and the two or more macro groups may be generated based on layer information included in the connection relationship information.

Abstract: Disclosed is a method for placing a semiconductor cell, which is performed by a computing device, and the method may include: determining a placement location of a macro cell in a design area using a reinforcement learning model; determining a candidate direction for shifting the placement location of the macro cell determined by the reinforcement learning model; and shifting the placement location of the macro cell based on the determined candidate direction, and the determined candidate direction may include a direction facing an outside of the design area.

Abstract: Disclosed is a method for placing a semiconductor device performed by a computing device according to an exemplary embodiment of the present disclosure.

Abstract: Disclosed is a method for designing an integrated circuit. Specifically, according to the present disclosure, a computing device identifies devices of the same type arranged in a design area, divides a device set including devices of the same type into a first subset and a second subset, rearranges devices included in the first subset based on a location of a connection site included in each device, and rearranges devices included in the second subset based on the rearranged devices included in the first subset.

Abstract: Disclosed is a method of performing double clustering to evaluate placement of semiconductor devices performed by a computing device according to an exemplary embodiment of the present disclosure. The method includes receiving connection relationship information representing a connection relationship between semiconductor devices, perform clustering on the semiconductor devices by utilizing first reference information based on the connection relationship information, and perform sub-clustering in a cluster generated by the clustering, by utilizing second reference information based on the connection relationship information.

Abstract: Disclosed is a method for automating a semiconductor design based on artificial intelligence, which is performed by a computing device. The method may include: receiving feature information and logical design information of a semiconductor element; and training a neural network model to place semiconductor elements in a canvas in an order by a large size based on the feature information and the logical design information.

Abstract: Disclosed is a method for automating a semiconductor design based on artificial intelligence, which is performed by a computing device. The method may include: generating a first embedding for a semiconductor element to be placed in a canvas based on feature information and logical design information of the semiconductor element by using a first neural network; and generating a probability distribution for placing the semiconductor element based on the first embedding and a second embedding for semiconductor elements already placed in the canvas by using a second neural network.

Abstract: Disclosed is a method of placing a semiconductor device, the method being performed by a computing device, the method including: receiving information about a prohibited area designated so that a semiconductor device is not placed; and training a neural network model to place a semiconductor device based on characteristic information of the semiconductor device and the information about the prohibited area.

Abstract: Disclosed is a method for automating a semiconductor design based on artificial intelligence, which is performed by a computing device. The method may include: generating a first embedding for a semiconductor element to be placed in a canvas based on feature information and logical design information of the semiconductor element by using a first neural network; and generating a probability distribution for placing the semiconductor element based on the first embedding and a second embedding for semiconductor elements already placed in the canvas by using a second neural network.

Abstract: Disclosed is a method for automating a semiconductor design based on artificial intelligence, which is performed by a computing device. The method may include: receiving feature information and logical design information of a semiconductor element; and training a neural network model to place semiconductor elements in a canvas in an order by a large size based on the feature information and the logical design information.