Patents by Inventor Jiyoon LIM

Jiyoon LIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12008297
    Abstract: Disclosed is a method of performing double clustering to evaluate placement of semiconductor devices performed by a computing device according to an exemplary embodiment of the present disclosure. The method includes receiving connection relationship information representing a connection relationship between semiconductor devices, perform clustering on the semiconductor devices by utilizing first reference information based on the connection relationship information, and perform sub-clustering in a cluster generated by the clustering, by utilizing second reference information based on the connection relationship information.
    Type: Grant
    Filed: January 23, 2024
    Date of Patent: June 11, 2024
    Assignee: MakinaRocks Co., Ltd.
    Inventors: Wooshik Myung, Jiyoon Lim, Seungju Kim, Wonjun Yoo
  • Patent number: 11790136
    Abstract: Disclosed is a method for automating a semiconductor design based on artificial intelligence, which is performed by a computing device. The method may include: receiving feature information and logical design information of a semiconductor element; and training a neural network model to place semiconductor elements in a canvas in an order by a large size based on the feature information and the logical design information.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: October 17, 2023
    Assignee: MakinaRocks Co., Ltd.
    Inventors: Jinwoo Park, Wooshik Myung, Kyeongmin Woo, Jiyoon Lim
  • Patent number: 11734484
    Abstract: Disclosed is a method for automating a semiconductor design based on artificial intelligence, which is performed by a computing device. The method may include: generating a first embedding for a semiconductor element to be placed in a canvas based on feature information and logical design information of the semiconductor element by using a first neural network; and generating a probability distribution for placing the semiconductor element based on the first embedding and a second embedding for semiconductor elements already placed in the canvas by using a second neural network.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: August 22, 2023
    Assignee: MAKINAROCKS CO., LTD.
    Inventors: Jinwoo Park, Wooshik Myung, Kyeongmin Woo, Jiyoon Lim
  • Patent number: 11663390
    Abstract: Disclosed is a method of placing a semiconductor device, the method being performed by a computing device, the method including: receiving information about a prohibited area designated so that a semiconductor device is not placed; and training a neural network model to place a semiconductor device based on characteristic information of the semiconductor device and the information about the prohibited area.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: May 30, 2023
    Assignee: MakinaRocks Co., Ltd.
    Inventor: Jiyoon Lim
  • Publication number: 20230153492
    Abstract: Disclosed is a method for automating a semiconductor design based on artificial intelligence, which is performed by a computing device. The method may include: receiving feature information and logical design information of a semiconductor element; and training a neural network model to place semiconductor elements in a canvas in an order by a large size based on the feature information and the logical design information.
    Type: Application
    Filed: November 14, 2022
    Publication date: May 18, 2023
    Applicant: MakinaRocks Co., Ltd.
    Inventors: Jinwoo PARK, Wooshik MYUNG, Kyeongmin WOO, Jiyoon LIM
  • Publication number: 20230153506
    Abstract: Disclosed is a method for automating a semiconductor design based on artificial intelligence, which is performed by a computing device. The method may include: generating a first embedding for a semiconductor element to be placed in a canvas based on feature information and logical design information of the semiconductor element by using a first neural network; and generating a probability distribution for placing the semiconductor element based on the first embedding and a second embedding for semiconductor elements already placed in the canvas by using a second neural network.
    Type: Application
    Filed: November 14, 2022
    Publication date: May 18, 2023
    Applicant: MakinaRocks Co., Ltd.
    Inventors: Jinwoo PARK, Wooshik MYUNG, Kyeongmin WOO, Jiyoon LIM