Patents by Inventor Jiyoun Kim

Jiyoun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200402304
    Abstract: An electronic device according to various embodiments may comprise: a display; a camera module; a memory; and a processor, wherein the processor is configured to obtain a selfie image, generate a user avatar on the basis of the obtained selfie image, reprocess the user avatar to generate at least one custom object interworking with applications of the electronic device, and while an application is executed, output the at least one custom object on a screen where the application is executed. Various other embodiments are also possible.
    Type: Application
    Filed: February 25, 2019
    Publication date: December 24, 2020
    Inventors: Hoik HWANG, Jiyoun KIM, Ohyoon KWON, Saebyuk SHEEN, Jaehan LEE, Junho CHOI
  • Patent number: 8863055
    Abstract: A method and apparatus to provide a capacitance to a design an integrated circuit is described. In one embodiment, the method receive a layout of the integrated circuit and applying canonical hierarchical models to the layout, wherein the canonical hierarchical models include a first type canonical model to capture a first capacitance of a device having a plurality of first conductors and a second type canonical model to capture a second capacitance between at least a portion of the device and one or more second conductors of the integrated circuit. The method further includes determining a capacitance for the layout based on the applying.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: October 14, 2014
    Assignee: Synopsys, Inc.
    Inventors: Arthur Nieuwoudt, Jiyoun Kim, Mathew Koshy, Baribrata Biswas
  • Publication number: 20130339915
    Abstract: A method and apparatus to provide a capacitance to a design an integrated circuit is described. In one embodiment, the method receive a layout of the integrated circuit and applying canonical hierarchical models to the layout, wherein the canonical hierarchical models include a first type canonical model to capture a first capacitance of a device having a plurality of first conductors and a second type canonical model to capture a second capacitance between at least a portion of the device and one or more second conductors of the integrated circuit. The method further includes determining a capacitance for the layout based on the applying.
    Type: Application
    Filed: August 21, 2013
    Publication date: December 19, 2013
    Applicant: Synopsys, Inc.
    Inventors: Arthur Nieuwoudt, Jiyoun Kim, Mathew Koshy, Baribrata Biswas
  • Patent number: 8522181
    Abstract: A technology specific information to design the integrated circuit is received. A plurality of canonical hierarchical models to capture an integrated circuit capacitance are created. The plurality of canonical hierarchical models includes at least a canonical model to capture a capacitance of a device having a plurality of conductors, and a canonical model to capture a capacitance between at least a portion of the device and one or more other conductors of the integrated circuit. The canonical hierarchical models can be applied to a layout of the integrated circuit. A capacitance for the layout can be determined based on the canonical hierarchical models.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: August 27, 2013
    Assignee: Synopsys, Inc.
    Inventors: Arthur Nieuwoudt, Jiyoun Kim, Mathew Koshy, Baribrata Biswas
  • Publication number: 20130191798
    Abstract: A technology specific information to design the integrated circuit is received. A plurality of canonical hierarchical models to capture an integrated circuit capacitance are created. The plurality of canonical hierarchical models includes at least a canonical model to capture a capacitance of a device having a plurality of conductors, and a canonical model to capture a capacitance between at least a portion of the device and one or more other conductors of the integrated circuit. The canonical hierarchical models can be applied to a layout of the integrated circuit. A capacitance for the layout can be determined based on the canonical hierarchical models.
    Type: Application
    Filed: January 24, 2012
    Publication date: July 25, 2013
    Inventors: Arthur Nieuwoudt, Jiyoun Kim, Mathew Koshy, Baribrata Biswas
  • Publication number: 20060233745
    Abstract: The present invention relates to devices, systems and methods for treating tumors. In particular, the present invention relates to enclosures housing cell-coated supports for promoting regression of tumors, such as cancerous tumors, papillomas, and warts. In preferred embodiments, the present invention provides methods of promoting tumor regression employing enclosures secreting therapeutic proteins.
    Type: Application
    Filed: December 12, 2005
    Publication date: October 19, 2006
    Applicant: Regents of the University of Michigan
    Inventors: Riley Rees, Jiyoun Kim, Daniel Remick, Belinda Adamson
  • Patent number: 7056503
    Abstract: The present invention relates to devices, systems and methods for treating tumors. In particular, the present invention relates to enclosures housing cell-coated supports for promoting regression of tumors, such as cancerous tumors, papillomas, and warts. In preferred embodiments, the present invention provides methods of promoting tumor regression employing enclosures secreting therapeutic proteins.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: June 6, 2006
    Assignee: Regents of the University of Michigan
    Inventors: Riley Rees, Jiyoun Kim, Daniel Remick, Belinda Adamson
  • Patent number: 7047506
    Abstract: A method is provided to speed up timing optimization after placement by parallelizing the optimization step. The method includes performing multiple partitions in the set of timing critical paths such that each partition can be optimized independently in a separate processor. To eliminate the need for inter-processor communication, conditions of timing independence and physical independence are imposed on each partition, thereby defining sub-sets of endpoints and paths associated therewith. The optimizing is performed in parallel by the processors, each of the processors optimizing timing of the paths associated with the endpoints in respective sub-sets. In a preferred embodiment, an endpoint graph is constructed from the list of critical paths, where the endpoint graph has at least one vertex representing critical paths associated with a given endpoint. The partitioning step then includes the step of partitioning the endpoint graph to define sub-sets of vertices.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: May 16, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jose Luis Pontes Corrcia Neves, Jiyoun Kim
  • Publication number: 20050108665
    Abstract: A method is provided to speed up timing optimization after placement by parallelizing the optimization step. The method includes performing multiple partitions in the set of timing critical paths such that each partition can be optimized independently in a separate processor. To eliminate the need for inter-processor communication, conditions of timing independence and physical independence are imposed on each partition, thereby defining sub-sets of endpoints and paths associated therewith. The optimizing is performed in parallel by the processors, each of the processors optimizing timing of the paths associated with the endpoints in respective sub-sets. In a preferred embodiment, an endpoint graph is constructed from the list of critical paths, where the endpoint graph has at least one vertex representing critical paths associated with a given endpoint. The partitioning step then includes the step of partitioning the endpoint graph to define sub-sets of vertices.
    Type: Application
    Filed: November 19, 2003
    Publication date: May 19, 2005
    Applicant: International Business Machines Corporation
    Inventors: Jose Luis Neves, Jiyoun Kim
  • Publication number: 20030007955
    Abstract: The present invention relates to devices, systems and methods for treating tumors. In particular, the present invention relates to enclosures housing cell-coated supports for promoting regression of tumors, such as cancerous tumors, papillomas, and warts. In preferred embodiments, the present invention provides methods of promoting tumor regression employing enclosures secreting therapeutic proteins.
    Type: Application
    Filed: September 25, 2001
    Publication date: January 9, 2003
    Inventors: Riley Rees, Jiyoun Kim, Daniel Remick, Belinda Adamson
  • Patent number: D890774
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jiyeon Kim, Jiyoun Kim, Saebyuk Shin, Jaehan Lee, Nari Choi, Hoik Hwang, Junho Choi