Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for managing access counts of wordlines of a memory. Repeated access to an aggressor wordline may cause increased data degradation in nearby victim wordlines of the memory. The access count of a given wordline may be stored in counter memory cells positioned along that wordline. When the wordline is accessed, the counter memory cells may be read out to refresh circuit, which may determine the access count based on the values stored in the counter memory cells. If the access count is below a threshold, the access count may be incremented and written back to the counter memory cells. If the access count is above the threshold, the refresh circuit may signal that the accessed wordline is an aggressor, and may reset the value of the access count before writing it back to the counter memory cells.

Abstract: Methods, systems, and devices for a compression method for defect visibility in a memory device are described. A memory device may identify one or more errors associated with a set of memory cells of a memory array in the device based on a first set of data associated with the first set of memory cells. The memory device may generate an indication of a location of the one or more errors in the first set of memory cells and compress the first set of data to generate an error flag based on identifying the one or more errors. The memory device may output the error flag and the indication of the location based on generating the error flag and the indication.

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/?1) at a faster rate than counts for more distant victim rows (e.g., +/?2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for lossy row access counting. Row addresses along a to address bus may be sampled. When the row address is sampled it may be compared to a plurality of stored addresses in a data storage unit. If the sampled address matches one of the stored addresses, a count value associated with that address may be updated in a first direction (such as being increased). Periodically, all of the count values may also be updated in a second direction (for example, decreased).

Abstract: Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/?1) at a faster rate than counts for more distant victim rows (e.g., +/?2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Abstract: An example apparatus includes an array of memory cells. Each memory cell includes an access device. Each access device includes a first source/drain region, a second source/drain region, and a gate opposing a channel connecting the first source/drain region and the second source/drain region. Each access device further includes a storage node. The example apparatus further includes a plurality of sense lines coupled to the first source/drain region of a different respective memory cell of the array of memory cells. The example apparatus further includes a plurality of access lines, wherein each access line includes at least one conductive pathway formed between the access line and a source/drain region of an access device coupled to the access line. The example apparatus further includes a shunt sense line coupled to the additional access device where the conductive pathway is formed.

Abstract: Some embodiments include an integrated assembly having first conductive lines which extend along a first direction, and having second conductive lines over the first conductive lines and which extend along a second direction that crosses the first direction. Capacitors are over the second conductive lines. The second conductive lines are operatively proximate active structures to gatedly couple a first set of the capacitors to the first conductive lines through the active structures. Shield structures are between the first conductive lines and extend along the first direction. A voltage source is electrically coupled to the shield structures through a second set of the capacitors. Some embodiments include assemblies having two or more decks stacked one atop another.

Abstract: Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.

Abstract: Some embodiments include an integrated assembly having a first digit line coupled with SENSE AMPLIFIER circuitry. The first digit line has a first region distal from the SENSE AMPLIFIER circuitry. A second digit line is coupled with the SENSE AMPLIFIER circuitry and has a second region distal from the SENSE AMPLIFIER circuitry. PRECHARGE circuitry includes one or more first equalization transistors proximate the first and second regions, and includes a second equalization transistor proximate the SENSE AMPLIFIER circuitry. Some embodiments include an integrated assembly having a first digit line coupled with SENSE AMPLIFIER circuitry. The first digit line has a first region distal from the SENSE AMPLIFIER circuitry. A second digit line is coupled with the SENSE AMPLIFIER circuitry and has a second region distal from the SENSE AMPLIFIER circuitry. PRECHARGE circuitry includes an electrical connection coupling the first and second regions to one another.

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Abstract: Some embodiments include an integrated assembly having a second deck over a first deck. A first true digit line has first and second segments along the first deck. A first complementary digit line has third and fourth segments along the second deck. The first true digit line is comparatively compared to the first complementary digit line. A second true digit line has a third region along the first deck and a fourth region along the second deck. The third region is adjacent the first segment, and the fourth region is adjacent the third segment. A second complementary digit line has a fifth region along the first deck and has a sixth region along the second deck. The fifth region is adjacent the second segment, and the sixth region is adjacent the fourth segment. The second true digit line is comparatively compared to the second complementary digit line.

Abstract: Some embodiments include an integrated assembly having a first deck, and having a second deck over the first deck. A first true digit line has a first region along the first deck, and has a second region along the second deck. A first complementary digit line has a first region along the first deck, and has a second region along the second deck. The first true digit line is comparatively compared to the first complementary digit line through SENSE AMPLIFIER circuitry. A second digit line has a first region along the first deck and laterally adjacent the first region of the first complementary digit line, and has a second region along the second deck and laterally adjacent the second region of the first true digit line.

Abstract: An example apparatus includes an array of memory cells. Each memory cell includes an access device. Each access device includes a first source/drain region, a second source/drain region, and a gate opposing a channel connecting the first source/drain region and the second source/drain region. Each access device further includes a storage node. The example apparatus further includes a plurality of sense lines coupled to the first source/drain region of a different respective memory cell of the array of memory cells. The example apparatus further includes a plurality of access lines, wherein each access line includes at least one conductive pathway formed between the access line and a source/drain region of an access device coupled to the access line. The example apparatus further includes a shunt sense line coupled to the additional access device where the conductive pathway is formed.

Abstract: An exemplary memory includes a memory cell array configured to store a plurality of data bits each associated with a respective column plane, and an input/output circuit including a compression circuit configured to provide error data based on a comparison between a bit of the plurality of data bits received from the memory cell array and an expected value and based on a respective column plane of the memory cell array with which the bit is associated. The compression circuit is further configured to encode a column plane error code based on the error data for provision to a data terminal.

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for lossy row access counting. Row addresses along a to address bus may be sampled. When the row address is sampled it may be compared to a plurality of stored addresses in a data storage unit. If the sampled address matches one of the stored addresses, a count value associated with that address may be updated in a lust direction (such as being increased). Periodically, all of the count values may also be updated in a second direction (for example, decreased).

Abstract: Some embodiments include an integrated assembly having first memory cells in a first array and second memory cells in a second array. First and second digit lines extend along columns of the first and second arrays, respectively. The first digit lines are comparatively coupled with the second digit lines through sense-amplifier-circuitry. The sense-amplifier-circuitry is distributed amongst at least two patch locations. A first of the patch locations has a first portion of the sense-amplifier-circuitry and has a first local column-select-structure. A second of the patch locations has a second portion of the sense-amplifier-circuitry and has a second local column-select-structure. A column-select-bus extends from decoder-circuitry to the first and second local column-select-structures. The column-select-bus is selectively coupled to the first and second local column-select-structures through first and second switches, respectively.

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/?1) at a faster rate than counts for more distant victim rows (e.g., +/?2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.