Abstract: The invention introduces an apparatus for generating a storage mapping table at least including a direct memory access controller for reading first physical location (PL) address corresponding to a logical location of the storage mapping table; an expanding circuit for obtaining the first PL address and expanding the first PL address into second PL address by appending data bits that originally provide different information from a physical address of the flash memory unit to the first PL address; and a controller for transmitting the second PL address without transmitting the first PL address stored in the flash memory unit to a host.

Abstract: A method and apparatus for performing automatic power control in a memory device are provided. The method includes: during an initialization phase of the memory device, performing signal level detection on a reference clock request signal to determine whether the reference clock request signal is at a first predetermined voltage level or a second predetermined voltage level, for performing the automatic power control for the memory device, wherein the reference clock request signal is received through an IO pad; and according to a logic value carried by an input signal of a selective regulation circuit (SRC), performing selective power control to generate a secondary power voltage according to a main power voltage, wherein the selective power control makes the secondary power voltage be either equal to the main power voltage or a regulated voltage of the main power voltage in response to the logic value carried by the input signal.

Abstract: A method and apparatus for performing automatic power control in a memory device are provided. The method includes: during an initialization phase of the memory device, performing signal level detection on a reference clock request signal to determine whether the reference clock request signal is at a first predetermined voltage level or a second predetermined voltage level, for performing the automatic power control for the memory device, wherein the reference clock request signal is received through an IO pad; and according to a logic value carried by an input signal of a selective regulation circuit (SRC), performing selective power control to generate a secondary power voltage according to a main power voltage, wherein the selective power control makes the secondary power voltage be either equal to the main power voltage or a regulated voltage of the main power voltage in response to the logic value carried by the input signal.

Abstract: The invention introduces an apparatus for generating a storage mapping table at least including a direct memory access controller for reading first physical location (PL) address corresponding to a logical location of the storage mapping table; an expanding circuit for obtaining the first PL address and expanding the first PL address into second PL address by appending data bits that originally provide different information from a physical address of the flash memory unit to the first PL address; and a controller for transmitting the second PL address without transmitting the first PL address stored in the flash memory unit to a host.

Abstract: The invention introduces an apparatus for generating a storage mapping table at least including a direct memory access controller for reading first physical location (PL) information corresponding to a logical location of the storage mapping table; an expanding circuit for obtaining the first PL information and expanding the first PL information into second PL information; and a controller for transmitting the second PL information to a host.

Abstract: A data processing circuit includes a condition input circuit and a search engine array. The condition input circuit receives and stores multiple search conditions corresponding to multiple data search tasks. The search engine array receives the search conditions and performs the data search tasks in a parallel manner according to the search conditions. The search engine array includes a storage medium and multiple search engines. The search condition(s) corresponding to one data search task is provided to one search engine and the search engine array accesses a random access memory to load the data stored in the random access memory into the storage medium. The search engines search the data stored in the storage medium according to the corresponding search condition(s) to perform the corresponding data search task, concurrently, and obtain a corresponding search result.

Abstract: The invention introduces an apparatus for generating a storage mapping table at least including a direct memory access controller for reading first physical location (PL) information corresponding to a logical location of the storage mapping table; an expanding circuit for obtaining the first PL information and expanding the first PL information into second PL information; and a controller for transmitting the second PL information to a host.

Abstract: A memory controller coupled between an external device and a memory is provided. The memory controller is coupled to the external device via a second interface and coupled to the memory via a first interface. The memory controller further includes a control logic to control the first interface and the second interface. The control logic sets the second interface to be at a receiving mode to receive a test data from the external device, and sets the first interface to be at a transmitting mode to transmit the test data to the memory. After a predetermined time, the control logic sets the first interface to be at the receiving mode to receive a test result from the memory, and sets the second interface to be at a transmitting mode to transmit the test result to the external device.

Abstract: A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is disclosed. The first transmittal module includes a specific pin. The clock pin receives a clock signal. The first transmittal module and the clock pin constitute an embedded multimedia card (eMMC) interface. The second transmittal module and the clock pin constitute a universal flash storage (UFS) interface. The first control module communicates with an external host via the first transmittal module according to the clock signal when a level of the specific pin is at a first level. The second control module communicates with the external host via the second transmittal module according to the clock signal when the level of the specific pin is at a second level. The first level exceeds the second level.

Abstract: A storage device including a processor, a controller, and a switch is provided. The processor is configured to control a logic circuit. When a main reset signal is enabled, the processor generates a sub-reset signal according to the operation status of the logic circuit. The controller generates a mask signal according to the main reset signal and the sub-reset signal. When the mask signal is enabled, the switch does not transmit the main reset signal to the logic circuit. When the mask signal is not enabled, the switch transmits the main reset signal to the logic circuit to reset the logic circuit.

Abstract: A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is disclosed. The first transmittal module includes a specific pin. The clock pin receives a clock signal. The first transmittal module and the clock pin constitute an embedded multimedia card (eMMC) interface. The second transmittal module and the clock pin constitute a universal flash storage (UFS) interface. The first control module communicates with an external host via the first transmittal module according to the clock signal when a level of the specific pin is at a first level. The second control module communicates with the external host via the second transmittal module according to the clock signal when the level of the specific pin is at a second level. The first level exceeds the second level.

Abstract: A control device coupled between a first memory and a second memory and including an execution unit, a first storage unit, a second storage unit, a selection unit and a processing unit is disclosed. The execution unit executes a specific instruction set to access the first and the second memories. The first storage unit is configured to store a first instruction set. The second storage unit is configured to store a second instruction set. The selection unit outputs one of the first and the second instruction sets to serve as the specific instruction set according to a control signal. The processing unit generates the control signal according to an execution state of the execution unit.

Abstract: A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is disclosed. The first transmittal module includes a specific pin. The clock pin receives a clock signal. The first transmittal module and the clock pin constitute an embedded multimedia card (eMMC) interface. The second transmittal module and the clock pin constitute a universal flash storage (UFS) interface. The first control module communicates with an external host via the first transmittal module according to the clock signal when a level of the specific pin is at a first level. The second control module communicates with the external host via the second transmittal module according to the clock signal when the level of the specific pin is at a second level. The first level exceeds the second level.

Abstract: A data processing circuit includes a condition input circuit and a search engine array. The condition input circuit receives and stores multiple search conditions corresponding to multiple data search tasks. The search engine array receives the search conditions and performs the data search tasks in a parallel manner according to the search conditions. The search engine array includes a storage medium and multiple search engines. The search condition(s) corresponding to one data search task is provided to one search engine and the search engine array accesses a random access memory to load the data stored in the random access memory into the storage medium. The search engines search the data stored in the storage medium according to the corresponding search condition(s) to perform the corresponding data search task, concurrently, and obtain a corresponding search result.

Abstract: A storage device including a processor, a controller, and a switch is provided. The processor is configured to control a logic circuit. When a main reset signal is enabled, the processor generates a sub-reset signal according to the operation status of the logic circuit. The controller generates a mask signal according to the main reset signal and the sub-reset signal. When the mask signal is enabled, the switch does not transmit the main reset signal to the logic circuit. When the mask signal is not enabled, the switch transmits the main reset signal to the logic circuit to reset the logic circuit.

Abstract: A memory controller coupled between an external device and a memory is provided. The memory controller is coupled to the external device via a second interface and coupled to the memory via a first interface. The memory controller further includes a control logic to control the first interface and the second interface. The control logic sets the second interface to be at a receiving mode to receive a test data from the external device, and sets the first interface to be at a transmitting mode to transmit the test data to the memory. After a predetermined time, the control logic sets the first interface to be at the receiving mode to receive a test result from the memory, and sets the second interface to be at a transmitting mode to transmit the test result to the external device.

Abstract: A storage unit coupled to a controller for receiving a first control signal and a second control signal is provided. The storage unit includes a cell array, a first access module and a second access module. The cell array stores data. The first access module accesses the data stored in the cell array according to the first control signal. The second access module processes the data stored in the cell array according to the second control signal to generate a search result and provides the search result to the controller. When the first access module receives the first control signal and the second access module receives the second control signal, the first and second access modules simultaneously operate.

Abstract: A memory controller is coupled to a memory device including a first block and a second block and includes a first register module, a first execution unit and a second register module. The first register module includes a plurality of set registers to store a first configuration file and a second configuration file. The first execution unit computes data stored in the first block simultaneously according to the first and the second configuration files to generate a first computation result and a computation operation result. The second register module includes a plurality of result registers to store the first and the second computation results.

Abstract: A control device coupled between a first memory and a second memory and including an execution unit, a first storage unit, a second storage unit, a selection unit and a processing unit is disclosed. The execution unit executes a specific instruction set to access the first and the second memories. The first storage unit is configured to store a first instruction set. The second storage unit is configured to store a second instruction set. The selection unit outputs one of the first and the second instruction sets to serve as the specific instruction set according to a control signal. The processing unit generates the control signal according to an execution state of the execution unit.

Abstract: A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is disclosed. The first transmittal module includes a specific pin. The clock pin receives a clock signal. The first transmittal module and the clock pin constitute an embedded multimedia card (eMMC) interface. The second transmittal module and the clock pin constitute a universal flash storage (UFS) interface. The first control module communicates with an external host via the first transmittal module according to the clock signal when a level of the specific pin is at a first level. The second control module communicates with the external host via the second transmittal module according to the clock signal when the level of the specific pin is at a second level. The first level exceeds the second level.