Patents by Inventor Jo Gyoo Chul

Jo Gyoo Chul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7442324
    Abstract: The present invention provides an etching agent that is able to etch a Cu film by a simple chemical etching method such as an immersion method when the low resistance Cu film is used for a wiring material, while allowing time-dependent changes of the etching rate to be small and preventing a pattern narrowing phenomenon ascribed to irregular amount of side etching of the Cu film from occurring, by providing an etching agent comprising an aqueous solution containing potassium hydrogen peroxosulfate and hydrofluoric acid, wherein masks of a give pattern is formed on the surface of a laminated film prepared by sequentially depositing a Ti or Ti alloy film and a Cu film on a substrate, and wherein a gate electrode (a laminated wiring) and a lower pad layer (a laminated wiring) with give patterns are formed by etching the laminated film using the etching agent having the foregoing construction.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: October 28, 2008
    Assignee: LG Display Co., Ltd.
    Inventors: Hitoshi Seki, Jo Gyoo Chul
  • Patent number: 7229569
    Abstract: The present invention provides an etching agent that is able to etch a Cu film by a simple chemical etching method such as an immersion method when the low resistance Cu film is used for a wiring material, while allowing time-dependent changes of the etching rate to be small and preventing a pattern narrowing phenomenon ascribed to irregular amount of side etching of the Cu film from occurring, by providing an etching agent comprising an aqueous solution containing potassium hydrogen peroxosulfate and hydrofluoric acid, wherein masks of a give pattern is formed on the surface of a laminated film prepared by sequentially depositing a Ti or Ti alloy film and a Cu film on a substrate, and wherein a gate electrode (a laminated wiring) and a lower pad layer (a laminated wiring) with give patterns are formed by etching the laminated film using the etching agent having the foregoing construction.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: June 12, 2007
    Assignee: LG. Philips LCD Co., Ltd.
    Inventors: Hitoshi Seki, Jo Gyoo Chul
  • Patent number: 6852998
    Abstract: A source line is directly connected to a source terminal composed of indium zinc oxide in a thin-film transistor substrate. A gate line is directly connected to a gate terminal composed of indium zinc oxide. Alternatively, drain electrodes of thin-film transistors for switching a plurality of pixel electrodes are directly connected to pixel electrodes composed of indium zinc oxide. These configurations do not require a passivation film which is essential for conventional thin-film transistor substrates, and the resulting thin-film transistor substrate can be made by a reduced number of manufacturing steps.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: February 8, 2005
    Assignee: LG Philips LCD Co., Ltd.
    Inventors: Chae Gee Sung, Jo Gyoo Chul, Makoto Sasaki, Kazuyuki Arai
  • Patent number: 6649936
    Abstract: A source line is directly connected to a source terminal composed of indium zinc oxide in a thin-film transistor substrate. A gate line is directly connected to a gate terminal composed of indium zinc oxide. Alternatively, drain electrodes of thin-film transistors for switching a plurality of pixel electrodes are directly connected to pixel electrodes composed of indium zinc oxide. These configurations do not require a passivation film which is essential for conventional thin-film transistor substrates, and the resulting thin-film transistor substrate can be made by a reduced number of manufacturing steps.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: November 18, 2003
    Assignee: LG. Philips LCD Co., Ltd.
    Inventors: Chae Gee Sung, Jo Gyoo Chul, Makoto Sasaki, Kazuyuki Arai
  • Publication number: 20030164498
    Abstract: A source line is directly connected to a source terminal composed of indium zinc oxide in a thin-film transistor substrate. A gate line is directly connected to a gate terminal composed of indium zinc oxide. Alternatively, drain electrodes of thin-film transistors for switching a plurality of pixel electrodes are directly connected to pixel electrodes composed of indium zinc oxide. These configurations do not require a passivation film which is essential for conventional thin-film transistor substrates, and the resulting thin-film transistor substrate can be made by a reduced number of manufacturing steps.
    Type: Application
    Filed: March 7, 2003
    Publication date: September 4, 2003
    Inventors: Chae Gee Sung, Jo Gyoo Chul, Makoto Sasaki, Kazuyuki Arai
  • Patent number: 6432755
    Abstract: A TFT structure having sufficiently low resistance wiring is provided, in which characteristic defects thereof caused by undercuts in a barrier metal layer can be prevented, the undercuts formed in a step for processing a source and a drain electrode composed of copper. The TFT structure of the present invention comprises a gate electrode on a glass substrate, a gate insulation film, a semiconductor active layer disposed on the gate insulation film so as to oppose the gate electrode, ohmic contact layers formed on both edge portions of the semiconductor active layer, and a source and a drain electrode connected to the semiconductor active layer via the respective ohmic contact layers. In addition, the source electrode and the drain electrode are formed of copper, and barrier metal layers are formed on the bottom surfaces of the source electrode and the drain electrode above areas at which the upper surfaces of the respective ohmic contact layers are located.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: August 13, 2002
    Assignee: LG. Philips LCD Co., Ltd.
    Inventors: Chae Gee Sung, Jo Gyoo Chul
  • Patent number: 6350995
    Abstract: A TFT structure having sufficiently low resistance wiring is provided. The present invention prevents the characteristic defects caused by undercuts in a barrier metal layer. In the prior art, the undercuts are formed by a step for processing a source and a drain electrode composed of copper. The TFT structure of the present invention comprises a gate electrode on a glass substrate, a gate insulation film, a semiconductor active layer disposed on the gate insulation film so as to oppose the gate electrode, ohmic contact layers formed on both edge portions of the semiconductor active layer, and a source and a drain electrode connected to the semiconductor active layer via the respective ohmic contact layers. In addition, the source electrode and the drain electrode are formed of copper. Barrier metal layers are formed on the bottom surfaces of the source electrode and the drain electrode above areas at which the upper surfaces of the respective ohmic contact layers are located.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: February 26, 2002
    Assignee: LG. Philips LCD Co., Ltd.
    Inventors: Chae Gee Sung, Jo Gyoo Chul
  • Publication number: 20020001887
    Abstract: A TFT structure having sufficiently low resistance wiring is provided, in which characteristic defects thereof caused by undercuts in a barrier metal layer can be prevented, the undercuts formed in a step for processing a source and a drain electrode composed of copper. The TFT structure of the present invention comprises a gate electrode on a glass substrate, a gate insulation film, a semiconductor active layer disposed on the gate insulation film so as to oppose the gate electrode, ohmic contact layers formed on both edge portions of the semiconductor active layer, and a source and a drain electrode connected to the semiconductor active layer via the respective ohmic contact layers. In addition, the source electrode and the drain electrode are formed of copper, and barrier metal layers are formed on the bottom surfaces of the source electrode and the drain electrode above areas at which the upper surfaces of the respective ohmic contact layers are located.
    Type: Application
    Filed: August 22, 2001
    Publication date: January 3, 2002
    Inventors: Chae Gee Sung, Jo Gyoo Chul