Patents by Inventor Joël Cambonie
Joël Cambonie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9323716Abstract: A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels include a first level including a first computation block including a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting mechanism, each computing node including an input port, a functional unit and an output port, the first connecting mechanism capable of connecting each output port to the input port of each other computing node; and a second level including a second computation block including a second data input, a second data output and a plurality of the first computation blocks interconnected by a second connecting means for selectively connecting the first data output of each of the first computation blocks and the second data input to each of the first data inputs and for selectively connecting each of the first data outputs to the second data output.Type: GrantFiled: July 11, 2014Date of Patent: April 26, 2016Assignee: STMICROELECTRONICS SAInventor: Joël Cambonie
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Publication number: 20140325181Abstract: A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels include a first level including a first computation block including a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting mechanism, each computing node including an input port, a functional unit and an output port, the first connecting mechanism capable of connecting each output port to the input port of each other computing node; and a second level including a second computation block including a second data input, a second data output and a plurality of the first computation blocks interconnected by a second connecting means for selectively connecting the first data output of each of the first computation blocks and the second data input to each of the first data inputs and for selectively connecting each of the first data outputs to the second data output.Type: ApplicationFiled: July 11, 2014Publication date: October 30, 2014Applicant: STMicroelectronics S.A.Inventor: Joël Cambonie
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Patent number: 8799623Abstract: A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels include a first level including a first computation block including a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting mechanism, each computing node including an input port, a functional unit and an output port, the first connecting mechanism capable of connecting each output port to the input port of each other computing node; and a second level including a second computation block including a second data input, a second data output and a plurality of the first computation blocks interconnected by a second connecting means for selectively connecting the first data output of each of the first computation blocks and the second data input to each of the first data inputs and for selectively connecting each of the first data outputs to the second data output.Type: GrantFiled: December 22, 2006Date of Patent: August 5, 2014Assignee: STMicroelectronics S.A.Inventor: Joël Cambonie
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Publication number: 20110107337Abstract: A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels include a first level including a first computation block including a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting mechanism, each computing node including an input port, a functional unit and an output port, the first connecting mechanism capable of connecting each output port to the input port of each other computing node; and a second level including a second computation block including a second data input, a second data output and a plurality of the first computation blocks interconnected by a second connecting means for selectively connecting the first data output of each of the first computation blocks and the second data input to each of the first data inputs and for selectively connecting each of the first data outputs to the second data output.Type: ApplicationFiled: December 22, 2006Publication date: May 5, 2011Applicant: STMicroelectronics S. A.Inventor: Joel Cambonie
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Patent number: 7633851Abstract: A circuit for generating a cyclic prefix of a symbol comprised of a sequence of time samples, the prefix being the reproduction of the last samples of the symbol at the beginning of the symbol, the symbol being obtained by inverse Fourier transform of complex coefficients corresponding to respective frequencies. The circuit includes a multiplier that shifts the phase of each complex coefficient by a value proportional to its frequency, a memory for storing the samples at the beginning of the symbol, and a multiplexer that copies at the end of the symbol the stored samples.Type: GrantFiled: January 21, 2004Date of Patent: December 15, 2009Assignee: STMicroelectronics S.A.Inventors: Simone Mazzoni, Joel Cambonie
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Patent number: 7594156Abstract: A circuit and a method for decoding data coded by blocks by a turbo-code including successive steps. One of the steps may use n first processors adapted to operating in parallel on n lines, or columns, of a block. Different steps may be performed in parallel on the same block of turbocoded data.Type: GrantFiled: December 19, 2002Date of Patent: September 22, 2009Inventors: Philippe Mejean, Joël Cambonie
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Patent number: 6992502Abstract: A configurable electronic circuit includes at least one tile that includes a plurality of cells interconnected. Each cell includes a multiplier, an arithmetic and logic unit for performing at least one arithmetic and/or logic function from a set of functions, a vertical bus, and a first configurable switching circuit connected to the vertical bus and to inputs of the multiplier. Each cell further includes a second configurable switching circuit connected to the vertical bus and to an output of the multiplier, a third configurable switching circuit connected to the vertical bus and to an output of the multiplier in a different cell, a fourth configurable switching circuit connected to the vertical bus and to inputs of the arithmetic and logic unit, and a fifth configurable switching circuit connected to the vertical bus and to an output of the arithmetic and logic unit.Type: GrantFiled: January 30, 2004Date of Patent: January 31, 2006Assignee: STMicroelectronics SAInventor: Joël Cambonie
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Patent number: 6960936Abstract: The configurable electronic device comprises a configurable electronic device includes at least one configurable basic assembly. The basic assembly includes a programmable circuit having a plurality of programmable elements, and a first configurable interconnection network for mutually connecting the programmable circuits. A plurality of configurable arithmetic cells are mutually connected by a second configurable interconnection network. A third configurable interconnection network links the programmable circuit and the configurable arithmetic cells. A control bus is between the programmable circuit and the configurable arithmetic cells, and also extends within the configurable arithmetic cells.Type: GrantFiled: February 3, 2004Date of Patent: November 1, 2005Assignee: STMicroelectronics SAInventor: Joël Cambonie
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Publication number: 20040225704Abstract: A configurable electronic circuit includes at least one tile that includes a plurality of cells interconnected. Each cell includes a multiplier, an arithmetic and logic unit for performing at least one arithmetic and/or logic function from a set of functions, a vertical bus, and a first configurable switching circuit connected to the vertical bus and to inputs of the multiplier. Each cell further includes a second configurable switching circuit connected to the vertical bus and to an output of the multiplier, a third configurable switching circuit connected to the vertical bus and to an output of the multiplier in a different cell, a fourth configurable switching circuit connected to the vertical bus and to inputs of the arithmetic and logic unit, and a fifth configurable switching circuit connected to the vertical bus and to an output of the arithmetic and logic unit.Type: ApplicationFiled: January 30, 2004Publication date: November 11, 2004Applicant: STMicroelectronics SAInventor: Joel Cambonie
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Publication number: 20040187088Abstract: The configurable electronic device comprises a configurable electronic device includes at least one configurable basic assembly. The basic assembly includes a programmable circuit having a plurality of programmable elements, and a first configurable interconnection network for mutually connecting the programmable circuits. A plurality of configurable arithmetic cells are mutually connected by a second configurable interconnection network. A third configurable interconnection network links the programmable circuit and the configurable arithmetic cells. A control bus is between the programmable circuit and the configurable arithmetic cells, and also extends within the configurable arithmetic cells.Type: ApplicationFiled: February 3, 2004Publication date: September 23, 2004Applicant: STMicroelectronics SAInventor: Joel Cambonie
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Publication number: 20040151110Abstract: A circuit for generating a cyclic prefix of a symbol comprised of a sequence of time samples, the prefix being the reproduction of the last samples of the symbol at the beginning of the symbol, the symbol being obtained by inverse Fourier transform of complex coefficients corresponding to respective frequencies. The circuit includes a multiplier that shifts the phase of each complex coefficient by a value proportional to its frequency, a memory for storing the samples at the beginning of the symbol, and a multiplexer that copies at the end of the symbol the stored samples.Type: ApplicationFiled: January 21, 2004Publication date: August 5, 2004Applicant: STMicroelectronics S.A.Inventors: Simone Mazzoni, Joel Cambonie
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Patent number: 6751642Abstract: Interleaved type processing includes a preprocessing phase in which for each initial symbol received an auxiliary symbol that includes N auxiliary complex samples is formulated, and a processing phase that includes for each auxiliary symbol an inverse Fourier transform calculation of size N. The processing phase includes elementary processing of the butterfly type corresponding to several stages of a general butterfly-like calculation graph. The various stages of the graph are implemented within a pipelined architecture. Upon receiving an initial symbol, two separate random access memories are simultaneously used to respectively store in a first memory the auxiliary symbol corresponding to this initial symbol, and to perform on the basis of the content of the second memory the elementary processing corresponding to a first stage of the graph. The two memories are swapped with each new receipt of an initial symbol.Type: GrantFiled: June 2, 2000Date of Patent: June 15, 2004Assignees: STMicroelectronics S.A., France TelecomInventors: Joël Cambonie, Philippe Mejean, Dominique Barthel, Joël Lienard, Simone Mazzoni
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Patent number: 6631167Abstract: The post-processing of the transformation processing of an interleaved type is temporally nested with regards to two successive symbols, and includes storage in two separately addressable memories of identical size. The addressing of the two memories is performed successively and alternately in the natural and reverse order at the frequency with the symbol clock signal.Type: GrantFiled: June 14, 2000Date of Patent: October 7, 2003Assignee: STMicroelectronics S.A.Inventors: Joël Cambonie, Philippe Mejean, Dominique Barthel, Joël Lienard
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Publication number: 20030126538Abstract: A circuit and a method for decoding data coded by blocks by a turbo-code including successive steps implementing different algorithms. At least two of the successive steps are capable of being applied in parallel to different data blocks.Type: ApplicationFiled: December 19, 2002Publication date: July 3, 2003Inventors: Philippe Mejean, Joel Cambonie
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Patent number: 6564236Abstract: A device includes a processor able to calculate the direct or inverse Fourier transform of the product of a complex input symbol of size N times a complex sinusoidal waveform of period n. The calculation is performed on the basis of elementary processes of the butterfly type corresponding to several stages of a general butterfly-shaped calculation graph where n is an integer less than N. The processor includes a first elementary processor able to simultaneously perform the multiplication and the Fourier transform calculations relating to the first stage of the graph.Type: GrantFiled: January 25, 2000Date of Patent: May 13, 2003Assignee: STMicroelectronics SAInventors: Joël Cambonie, Simone Mazzoni
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Patent number: 6408319Abstract: An electronic device for computing a Fourier transform having a pipeline architecture includes at least one processing stage with a radix equal to 4. Each processing stage includes elementary processing for performing process operations for Fourier transforms of size equal to 4 on data blocks. Each processing stage also includes an elementary storage that includes a random access memory. In particular, the random access memory is a single-access memory with a storage capacity equal to 3N/4 data bits. The size of the data block processed by this stage is equal to N.Type: GrantFiled: December 18, 1998Date of Patent: June 18, 2002Assignee: STMicroelectronics S.A.Inventor: Joel Cambonie
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Patent number: 6324561Abstract: For each input block of N data bits received as an input to a stage for computing a Fourier transform, only three quarters of the data bits of the input block are stored in a main storage. A Fourier transform computation is performed on the basis of the stored data and of the other data of the block. Only half of the data bits received are stored in an auxiliary storage. All the data bits of the input block are reconstructed from the contents of the main and auxiliary storage to obtain a reconstructed data block, which is temporally delayed with respect to the input block.Type: GrantFiled: December 18, 1998Date of Patent: November 27, 2001Assignee: STMicroelectronics S.A.Inventor: Joel Cambonie
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Patent number: 4873658Abstract: Integrated circuits capable of carrying out transformations of the "cosine transformation" type, used more particularly for the digital processing of images with a view to information compression. The versatile and compact circuit architecture involves dividing a bus into sections separated by switches actuated in phase opposition; certain sections are coupled to computing operators, whereas others are coupled to memories serving for reorganizing the order in which the data is presented to the following operators.Type: GrantFiled: December 21, 1987Date of Patent: October 10, 1989Assignee: SGS-Thomson Microelectronics S.A.Inventor: Joel Cambonie
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Patent number: 4872134Abstract: A signal-processing circuit performs a cosine type transformation (double addition in rows and columns) of values of a matrix of n rows and n columns. An architecture is proposed with a row transform circuit, a column transform circuit and a buffer memory of nxn words. The memory is addressed sequentially, line by line, during the storage of nxn coefficients C.sup.i (v) which are the results of the row transform on a block of nxn data. Then it is addressed sequentially, column by column, during the storage of nxn coefficients C.sup.i (v) corresponding to the processing of the following block. At each address, a read stage of a coefficient is performed followed by the writing of a new coefficient. The invention can be applied to circuits for the digital processing of images to prepare the compression of data before transmission.Type: GrantFiled: December 21, 1987Date of Patent: October 3, 1989Assignee: SGS Thomson Microelectronics S.A.Inventors: Joel Cambonie, Alain Artieri
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Patent number: RE34734Abstract: Integrated circuits capable of carrying out transformations of the "cosine transformation" type, used more particularly for the digital processing of images with a view to information compression. The versatile and compact circuit architecture involves dividing a bus into sections separated by switches actuated in phase opposition; certain sections are coupled to computing operators, whereas others are coupled to memories serving for reorganizing the order in which the data is presented to the following operators.Type: GrantFiled: October 10, 1991Date of Patent: September 20, 1994Assignee: SGS-Thomson Microelectronics, S.A.Inventor: Joel Cambonie