Abstract: The invention relates to a channel equalizing and decoding device consisting of a series of modules, each of which comprises an equalizer (10) and a decoder with weighted output (20). The modules of rank higher than 1 receive (i) a sequence of samples coming from a sensor and delayed by a value equal to the processing time of preceding modules and (ii) the output from the preceding module. Said invention is characterized in that each of the modules comprises means for receiving at least two different sequences of samples and an equalizer that can determine one same equalized sequence of samples using the aforementioned minimum two sequences received as two different non-equalized representations of the sequence of samples to be determined.

Abstract: An equalizer device is used for digital communications systems having a plurality of receive channels. The equalizer device in normal operation comprises a transversal filter for each receive channel, an adder for summing the receive channels, and a system downstream from the adder including a phase corrector and a recursive portion including a single recursive filter and decision circuit in its forward branch. The equalizer device including decision-taking circuit for evaluating its performance as a function of the output signal from the equalizer device and for responding to the result of this evaluation by switching from a first structure which corresponds to a normal mode of operation to a second structure which corresponds to a convergence mode of operation, and vice versa.

Abstract: Equalizing and decoding apparatus including a module which comprises an equalizer and a weighted output decoder, the apparatus being characterized in that it comprises a plurality of modules of said type in series, in which each equalizer has at least one transversal filter for reducing noise power and in which each module of rank greater than 1 also receives a stream of channel samples that has been delayed by a quantity equal to the processing time of the preceding modules.

Abstract: The equalizer circuit for the receiver of a digital communications system is characterized in that its predictor (11) is purely recursive, its phase equalizer (12) is purely transversal, and the relative positions of those two elements are interchangeable, means for evaluating performance in terms of decision error and for causing the two elements to be interchanged in application of a criterion for evaluating the difficulty of reception, the predictor being upstream and optimized in adaptive and self-learning manner to whiten its own output while the phase equalizer (12) is downstream and optimized in adaptive manner during periods of difficult reception, whereas the predictor (11) is downstream and the phase equalizer (12) is upstream, both being optimized jointly in adaptive manner to minimize decision error between the output (d(n)) of the decision circuit (2) and its input (w(n) or y(n)) during periods of easy reception.

Abstract: The invention concerns a device for recovering a carrier wave provided with a circuit for inhibiting dummy frequency hookings or acquisitions for phase-modulated digital signals in N states with a phase N=2P, device including a phase locking loop provided with demodulation, a voltage-controllable oscillator, a 90.degree. phase shifter, for the low-pass filtering of basic band signals X1(t) and Y1(t), a loop filter, for sampling the signals X1(t) and Y1(t) and having a sampling frequency Fe so that Fe>(2p+1.vertline.n.vertline.)/T where T is the reciprocal value of the modulation speed and, associated with this loop, a circuit for drawing up the filtered signals Sign Sin (2P .PHI.k) and Sign Cos (2P .PHI.k) required for detection of the direction of variation of the phase error, a phase/frequency comparator, loss of synchronization and hooking detection and an adaptive filter.