Patents by Inventor Jo Lin

Jo Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12243641
    Abstract: Provided herein is an engagement and care support platform (“ECSP”) computer system including at least one processor in communication with at least one memory device for facilitating senior user engagement. The processor is programmed to: (i) register a user through an application, (ii) register a caregiver associated with the user through the application, (iii) generate a senior profile based upon user personal and scheduling data, (iv) build a daily interactive user interface that reflects the senior profile, (v) display the daily interactive user interface at a first client device associated with the user, (vi) cause the first client device to initiate a daily interaction prompt to the user, (vii) determine whether any user interaction was received in response to the daily interaction prompt, and (viii) transmit a daily update message to a second client device associated with the caregiver, including an indication of whether any user interaction was received.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: March 4, 2025
    Assignee: State Farm Mutual Automobile Insurance Company
    Inventors: Michael DiBenedetto, Audrey Schwartz, Sydney Volk, Daniel Davidson, Daniel Wilson, Jo-Jo Lin, Zaki Goumandakoye
  • Publication number: 20250044329
    Abstract: Methods and systems for monitoring and analyzing electrical energy use at a site are disclosed herein. An electricity monitoring device configured to measure real-time electricity characteristics (e.g., instantaneous voltage levels) may be plugged into an outlet of an electrical circuit of a structure. The data obtained by such device may then be analyzed to determine electricity usage levels for the site and/or for individual electrical devices in the structure (e.g., based upon unique electrical signatures indicated by variations in voltage levels). The electricity usage levels may further be used to generate an energy use profile for the structure.
    Type: Application
    Filed: March 11, 2024
    Publication date: February 6, 2025
    Inventors: Christian Payne, Rick J. Campbell, Mike Hambleton, Tara Hayman, Jo-Jo Lin, Zaki Goumandakoye, Diana Sherwood, Joseph Harr
  • Publication number: 20240395566
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Publication number: 20240321733
    Abstract: An interconnection structure and methods of forming the same are described. The interconnection structure includes a dielectric layer, a dielectric material disposed over the dielectric layer, and first and second conductive features disposed in the dielectric material. The first and second conductive features each has rounded top corners, the first conductive feature has a first width and a first height, and the second conductive feature has a second width substantially less than the first width and a second height substantially the same as the first height. The structure further includes an etch stop layer disposed on the first and second conductive features and third and fourth conductive features disposed in the dielectric material and the etch stop layer. The third conductive feature is in contact with the first conductive feature, and the fourth conductive feature is in contact with the second conductive feature.
    Type: Application
    Filed: June 14, 2023
    Publication date: September 26, 2024
    Inventors: Chia-Pang KUO, Jo-Lin LAN, Chun Hsiang YANG, Ming-Yuan GAO, Chi-Feng LIN
  • Patent number: 12094728
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Publication number: 20240282628
    Abstract: A method of forming a semiconductor structure includes forming a seed layer on a substrate, forming a photoresist layer on the seed layer with a first opening wider than a second opening, performing an electroplating process with a first plating current to grow a bottom portion of a first metal line in the first opening and a bottom portion of a second metal line in the second opening, continuing the electroplating process with a second plating current that is larger than the first plating current to grow a top portion of the first metal line and a top portion of the second metal line, removing the photoresist layer to expose a portion of the seed layer, and removing the exposed portion of the seed layer.
    Type: Application
    Filed: July 25, 2023
    Publication date: August 22, 2024
    Inventors: Dian-Hau CHEN, Chen-Chiu HUANG, Hsiang-Ku SHEN, ShuFang CHEN, Ying-Yao LAI, Wen-Ling CHANG, Chi-Feng LIN, Peng-Chung JANGJIAN, Jo-Lin LAN, Fang-I Chih
  • Publication number: 20240038688
    Abstract: A device includes a molding compound, a plurality of through vias, a seal ring structure, and a protection layer. The plurality of through vias are embedded in the molding compound. The seal ring structure is over the molding compound and surrounds the through vias in a top view. The protection layer covers the seal ring and extends toward the molding compound in a cross-sectional view.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 1, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng LIU, Jo-Lin LAN, Yu-Hsiang HU, Hung-Jui KUO
  • Patent number: 11817399
    Abstract: A device includes a semiconductor chip, a molding compound, an insulating structure, an under-bump-metallurgy (UBM), a conductive ball, and a protection layer. The molding compound laterally surrounds the semiconductor chip. The insulating structure is over the semiconductor chip and the molding compound. The UBM is over the insulating structure and is electrically connected to the semiconductor chip. The conductive ball is in contact with the UBM. The protection layer extends from the UBM to the molding compound.
    Type: Grant
    Filed: June 6, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng Liu, Jo-Lin Lan, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20230307251
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 28, 2023
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 11699598
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: July 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Publication number: 20220246292
    Abstract: Provided herein is an engagement and care support platform (“ECSP”) computer system including at least one processor in communication with at least one memory device for facilitating senior user engagement. The processor is programmed to: (i) register a user through an application, (ii) register a caregiver associated with the user through the application, (iii) generate a senior profile based upon user personal and scheduling data, (iv) build a daily interactive user interface that reflects the senior profile, (v) display the daily interactive user interface at a first client device associated with the user, (vi) cause the first client device to initiate a daily interaction prompt to the user, (vii) determine whether any user interaction was received in response to the daily interaction prompt, and (viii) transmit a daily update message to a second client device associated with the caregiver, including an indication of whether any user interaction was received.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 4, 2022
    Inventors: Michael DiBenedetto, Audrey Schwartz, Sydney Volk, Daniel Davidson, Daniel Wilson, Jo-Jo Lin, Zaki Goumandakoye
  • Publication number: 20220245593
    Abstract: Provided herein is an engagement and care support platform (“ECSP”) computer system including at least one processor in communication with at least one memory device for facilitating senior user engagement. The processor is programmed to: (i) register a user through an application, (ii) register a caregiver associated with the user through the application, (iii) generate a senior profile based upon user personal and scheduling data, (iv) build a daily interactive user interface that reflects the senior profile, (v) display the daily interactive user interface at a first client device associated with the user, (vi) cause the first client device to initiate a daily interaction prompt to the user, (vii) determine whether any user interaction was received in response to the daily interaction prompt, and (viii) transmit a daily update message to a second client device associated with the caregiver, including an indication of whether any user interaction was received.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 4, 2022
    Inventors: Michael DiBenedetto, Audrey Schwartz, Sydney Volk, Daniel Davidson, Daniel Wilson, Jo-Jo Lin, Zaki Goumandakoye
  • Publication number: 20210296262
    Abstract: A device includes a semiconductor chip, a molding compound, an insulating structure, an under-bump-metallurgy (UBM), a conductive ball, and a protection layer. The molding compound laterally surrounds the semiconductor chip. The insulating structure is over the semiconductor chip and the molding compound. The UBM is over the insulating structure and is electrically connected to the semiconductor chip. The conductive ball is in contact with the UBM. The protection layer extends from the UBM to the molding compound.
    Type: Application
    Filed: June 6, 2021
    Publication date: September 23, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng LIU, Jo-Lin LAN, Yu-Hsiang HU, Hung-Jui KUO
  • Patent number: 11031351
    Abstract: A method includes forming an insulating film over a semiconductor structure, forming a sealing ring over a sidewall of the insulating film, and forming a protective layer over an exposed sidewall of the sealing ring. The semiconductor structure includes a semiconductor chip and a molding compound disposed around the semiconductor chip. The exposed sidewall of the sealing ring faces away from the sidewall of the insulating film.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng Liu, Jo-Lin Lan, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20210134611
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 6, 2021
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 10867811
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Publication number: 20190172796
    Abstract: A method includes forming an insulating film over a semiconductor structure, forming a sealing ring over a sidewall of the insulating film, and forming a protective layer over an exposed sidewall of the sealing ring. The semiconductor structure includes a semiconductor chip and a molding compound disposed around the semiconductor chip. The exposed sidewall of the sealing ring faces away from the sidewall of the insulating film.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 6, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng LIU, Jo-Lin LAN, Yu-Hsiang HU, Hung-Jui KUO
  • Patent number: 10304700
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Shih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 10204870
    Abstract: A method of manufacturing a semiconductor device includes: receiving a semiconductor structure having a chip region, a seal ring region surrounding the chip region, and a scribe region surroundingly defined around the seal ring region, the semiconductor structure including: a semiconductor chip in the chip region; and a molding compound disposed around the semiconductor chip and distributed in the chip region, the seal ring region and the scribe region; forming an insulating film over the chip region of the semiconductor structure and the seal ring region of the semiconductor structure; forming a seal ring over the seal ring region of the semiconductor structure and laterally adjacent to the insulating film, in which the seal ring has an exposed lateral surface facing away from the insulating film; and forming a protective layer that defines a substantially smooth and inclined lateral surface over the exposed lateral surface of the seal ring.
    Type: Grant
    Filed: October 8, 2016
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng Liu, Jo-Lin Lan, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20180350629
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Application
    Filed: July 31, 2018
    Publication date: December 6, 2018
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou