Patents by Inventor Jo-Lin Lan

Jo-Lin Lan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240038688
    Abstract: A device includes a molding compound, a plurality of through vias, a seal ring structure, and a protection layer. The plurality of through vias are embedded in the molding compound. The seal ring structure is over the molding compound and surrounds the through vias in a top view. The protection layer covers the seal ring and extends toward the molding compound in a cross-sectional view.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 1, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng LIU, Jo-Lin LAN, Yu-Hsiang HU, Hung-Jui KUO
  • Patent number: 11817399
    Abstract: A device includes a semiconductor chip, a molding compound, an insulating structure, an under-bump-metallurgy (UBM), a conductive ball, and a protection layer. The molding compound laterally surrounds the semiconductor chip. The insulating structure is over the semiconductor chip and the molding compound. The UBM is over the insulating structure and is electrically connected to the semiconductor chip. The conductive ball is in contact with the UBM. The protection layer extends from the UBM to the molding compound.
    Type: Grant
    Filed: June 6, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng Liu, Jo-Lin Lan, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20230307251
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 28, 2023
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 11699598
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: July 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Publication number: 20210296262
    Abstract: A device includes a semiconductor chip, a molding compound, an insulating structure, an under-bump-metallurgy (UBM), a conductive ball, and a protection layer. The molding compound laterally surrounds the semiconductor chip. The insulating structure is over the semiconductor chip and the molding compound. The UBM is over the insulating structure and is electrically connected to the semiconductor chip. The conductive ball is in contact with the UBM. The protection layer extends from the UBM to the molding compound.
    Type: Application
    Filed: June 6, 2021
    Publication date: September 23, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng LIU, Jo-Lin LAN, Yu-Hsiang HU, Hung-Jui KUO
  • Patent number: 11031351
    Abstract: A method includes forming an insulating film over a semiconductor structure, forming a sealing ring over a sidewall of the insulating film, and forming a protective layer over an exposed sidewall of the sealing ring. The semiconductor structure includes a semiconductor chip and a molding compound disposed around the semiconductor chip. The exposed sidewall of the sealing ring faces away from the sidewall of the insulating film.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng Liu, Jo-Lin Lan, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20210134611
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 6, 2021
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 10867811
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Publication number: 20190172796
    Abstract: A method includes forming an insulating film over a semiconductor structure, forming a sealing ring over a sidewall of the insulating film, and forming a protective layer over an exposed sidewall of the sealing ring. The semiconductor structure includes a semiconductor chip and a molding compound disposed around the semiconductor chip. The exposed sidewall of the sealing ring faces away from the sidewall of the insulating film.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 6, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng LIU, Jo-Lin LAN, Yu-Hsiang HU, Hung-Jui KUO
  • Patent number: 10304700
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Shih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 10204870
    Abstract: A method of manufacturing a semiconductor device includes: receiving a semiconductor structure having a chip region, a seal ring region surrounding the chip region, and a scribe region surroundingly defined around the seal ring region, the semiconductor structure including: a semiconductor chip in the chip region; and a molding compound disposed around the semiconductor chip and distributed in the chip region, the seal ring region and the scribe region; forming an insulating film over the chip region of the semiconductor structure and the seal ring region of the semiconductor structure; forming a seal ring over the seal ring region of the semiconductor structure and laterally adjacent to the insulating film, in which the seal ring has an exposed lateral surface facing away from the insulating film; and forming a protective layer that defines a substantially smooth and inclined lateral surface over the exposed lateral surface of the seal ring.
    Type: Grant
    Filed: October 8, 2016
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng Liu, Jo-Lin Lan, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20180350629
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Application
    Filed: July 31, 2018
    Publication date: December 6, 2018
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Publication number: 20170317034
    Abstract: A method of manufacturing a semiconductor device includes: receiving a semiconductor structure having a chip region, a seal ring region surrounding the chip region, and a scribe region surroundingly defined around the seal ring region, the semiconductor structure including: a semiconductor chip in the chip region; and a molding compound disposed around the semiconductor chip and distributed in the chip region, the seal ring region and the scribe region; forming an insulating film over the chip region of the semiconductor structure and the seal ring region of the semiconductor structure; forming a seal ring over the seal ring region of the semiconductor structure and laterally adjacent to the insulating film, in which the seal ring has an exposed lateral surface facing away from the insulating film; and forming a protective layer that defines a substantially smooth and inclined lateral surface over the exposed lateral surface of the seal ring.
    Type: Application
    Filed: October 8, 2016
    Publication date: November 2, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng LIU, Jo-Lin LAN, Yu-Hsiang HU, Hung-Jui KUO
  • Publication number: 20170110421
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Application
    Filed: June 1, 2016
    Publication date: April 20, 2017
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 8349394
    Abstract: A method of forming an electrode having an electrochemical catalyst layer is disclosed, which comprises providing a substrate with a conductive layer formed on the surface of a substrate, conditioning the surface of the substrate, immersing the substrate in a solution containing polymer-capped noble metal nanoclusters dispersed therein to form a polymer-protected electrochemical catalyst layer on the conditioned surface of the substrate, and thermally treating the polymer-protected electrochemical catalyst layer at a temperature approximately below 300° C.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: January 8, 2013
    Assignee: Tripod Technology Corporation
    Inventors: Chao Peng, Jo-Lin Lan, Ya-Huei Chang, Wen-Chi Hsu, Hai-Peng Cheng, Shien-Ping Feng, Wen-Hsiang Chen, Tzu-Chien Wei
  • Patent number: 8298434
    Abstract: A method of forming an electrode having an electrochemical catalyst layer is disclosed. The method includes etching a surface of a substrate, followed by immersing the substrate in a solution containing surfactants to form a conditioner layer on the surface of the substrate, and immersing the substrate in a solution containing polymer-capped noble metal nanoclusters dispersed therein to form a polymer-protected electrochemical catalyst layer on the conditioner layer.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: October 30, 2012
    Assignee: Tripod Technology Corporation
    Inventors: Tzu-Chien Wei, Hai-Peng Cheng, Shien-Ping Feng, Jo-Lin Lan, Chao Peng, Wen-Chi Hsu, Ya-Huei Chang, Wen-Hsiang Chen
  • Patent number: 8241372
    Abstract: A method of forming an electrode including an electrochemical catalyst layer is disclosed, which comprises forming a graphitized porous conductive fabric layer, optionally conditioning the graphitized porous conductive fabric layer, and dipping the graphitized porous conductive fabric layer into a solution containing a plurality of polymer-capped noble metal nanoclusters dispersed therein. The polymer-capped noble metal nanoclusters as an electrochemical catalyst layer are adsorbed onto the graphitized porous conductive fabric layer. An electrochemical device with the electrode made thereby is also contemplated.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: August 14, 2012
    Assignee: Tripod Technology Corporation
    Inventors: Hai-Peng Cheng, Shien-Ping Feng, Jo-Lin Lan, Chao Peng, Tzu-Chien Wei, Wen-Chi Hsu, Ya-Huei Chang, Wen-Hsiang Chen
  • Publication number: 20100108240
    Abstract: A method of forming an electrode having an electrochemical catalyst layer is disclosed. The method includes etching a surface of a substrate, followed by immersing the substrate in a solution containing surfactants to form a conditioner layer on the surface of the substrate, and immersing the substrate in a solution containing polymer-capped noble metal nanoclusters dispersed therein to form a polymer-protected electrochemical catalyst layer on the conditioner layer.
    Type: Application
    Filed: October 29, 2009
    Publication date: May 6, 2010
    Applicant: TRIPOD TECHNOLOGY CORPORATION
    Inventors: Tzu-Chien WEI, Hai-Peng CHENG, Shien-Ping FENG, Jo-Lin LAN, Chao PENG, Wen-Chi HSU, Ya-Huei CHANG, Wen-Hsiang CHEN
  • Publication number: 20100101644
    Abstract: Disclosed herein is a dye-sensitized solar cell. The dye-sensitized solar cell includes a semiconductor electrode with a dye adsorbed thereon; a counter electrode; and an electrolyte composition provided between the semiconductor electrode and the counter electrode; wherein the electrolyte composition comprises an oxidation-reduction mediator and a eutectic ionic liquid including a choline halide or derivatives thereof mixed with alcohols or urea.
    Type: Application
    Filed: October 23, 2009
    Publication date: April 29, 2010
    Applicant: TRIPOD TECHNOLOGY CORPORATION
    Inventors: Huei-Ru JHONG, Hai-Peng CHENG, Shien-Ping FENG, Jo-Lin LAN, Chao PENG, Tzu-Chien WEI, Wen-Chi HSU, Ya-Huei CHANG, Wen-Hsiang CHEN
  • Publication number: 20100101623
    Abstract: A packaging structure with a box for containing at least a portable electronic device is provided. The box has plates, which are connected to one another and surrounded to form an opening for the portable electronic device passing through, and a lid selectively covering or exposing the opening. First solar cells each fastened on an inner surface of each plate in the box. At least a cable electrically connects the first solar cells and is operated for electrically connecting the portable electronic device.
    Type: Application
    Filed: March 10, 2009
    Publication date: April 29, 2010
    Applicant: TRIPOD TECHNOLOGY CORPORATION
    Inventors: Tzu-Chien WEI, Chao PENG, Jo-Lin LAN, Ya-Huei CHANG, Wen-Chi HSU, Hai-Peng CHENG, Shien-Ping FENG, Wen-Hsiang CHEN