Patents by Inventor Jo-Mei Wang

Jo-Mei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Package structure and manufacturing method thereof
    Patent number: 10276542
    Abstract: A package structure has first and second dies, a molding compound, a first redistribution layer, at least one first through interlayer via (TIV), second through interlayer vias (TIVs), an electromagnetic interference shielding layer and conductive elements. The first die is molded in the molding compound. The second die is disposed on the molding compound. The first redistribution layer is located between the conductive elements and the molding compound and electrically connected to the first and second dies. The molding compound is located between the second die and the first redistribution layer. The first and second TIVs are molded in the molding compound and electrically connected to the first redistribution layer. The second TIVs are located between the first die and the first TIV. The electromagnetic interference shielding layer is in contact with the first TIV. The conductive elements are connected to the first redistribution layer.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen, Hua-Wei Tseng, Jo-Mei Wang, Tien-Chung Yang, Kuan-Chung Lu
  • Devices, packaging devices, and methods of packaging semiconductor devices
    Patent number: 10177032
    Abstract: Devices, packaging devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes a molding material and a plurality of through-vias disposed within the molding material. A dummy through-via and an integrated circuit die are also disposed within the molding material. An interconnect structure is disposed over the molding material, the plurality of through-vias, the dummy through-via, and the integrated circuit die.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, An-Jhih Su, Jo-Mei Wang
  • Package structures, pop devices and methods of forming the same
    Patent number: 9941248
    Abstract: Package structures, PoP devices and methods of forming the same are disclosed. A package structure includes a first chip, a redistribution layer structure, a plurality of UBM pads, a plurality of connectors and a separator. The redistribution layer structure is electrically connected to the first chip. The UBM pads are electrically connected to the redistribution layer structure. The connectors are electrically connected to the UBM pads. The separator is over the redistribution layer structure and surrounds the connectors.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tien-Chung Yang, An-Jhih Su, Hsien-Wei Chen, Jo-Mei Wang, Wei-Yu Chen
  • Wafer level shielding in multi-stacked fan out packages and methods of forming same
    Patent number: 9922939
    Abstract: An embodiment device package includes a device die, a molding compound surrounding the device die, a conductive through inter-via (TIV) extending through the molding compound, and an electromagnetic interference (EMI) shield disposed over and extending along sidewalls of the molding compound. The EMI shield contacts the conductive TIV, and the conductive TIV electrically connects the EMI shield to an external connector. The external connector and the EMI shield are disposed on opposing sides of the device die.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Hsien-Wei Chen, An-Jhih Su, Jo-Mei Wang, Tien-Chung Yang
  • PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20180026010
    Abstract: A package structure has first and second dies, a molding compound, a first redistribution layer, at least one first through interlayer via (TIV), second through interlayer vias (TIVs), an electromagnetic interference shielding layer and conductive elements. The first die is molded in the molding compound. The second die is disposed on the molding compound. The first redistribution layer is located between the conductive elements and the molding compound and electrically connected to the first and second dies. The molding compound is located between the second die and the first redistribution layer. The first and second TIVs are molded in the molding compound and electrically connected to the first redistribution layer. The second TIVs are located between the first die and the first TIV. The electromagnetic interference shielding layer is in contact with the first TIV. The conductive elements are connected to the first redistribution layer.
    Type: Application
    Filed: July 21, 2016
    Publication date: January 25, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen, Hua-Wei Tseng, Jo-Mei Wang, Tien-Chung Yang, Kuan-Chung Lu
  • PACKAGE STRUCTURES, POP DEVICES AND METHODS OF FORMING THE SAME
    Publication number: 20170345795
    Abstract: Package structures, PoP devices and methods of forming the same are disclosed. A package structure includes a first chip, a redistribution layer structure, a plurality of UBM pads, a plurality of connectors and a separator. The redistribution layer structure is electrically connected to the first chip. The UBM pads are electrically connected to the redistribution layer structure. The connectors are electrically connected to the UBM pads. The separator is over the redistribution layer structure and surrounds the connectors.
    Type: Application
    Filed: August 17, 2016
    Publication date: November 30, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tien-Chung Yang, An-Jhih Su, Hsien-Wei Chen, Jo-Mei Wang, Wei-Yu Chen
  • Wafer Level Shielding in Multi-Stacked Fan Out Packages and Methods of Forming Same
    Publication number: 20170256502
    Abstract: An embodiment device package includes a device die, a molding compound surrounding the device die, a conductive through inter-via (TIV) extending through the molding compound, and an electromagnetic interference (EMI) shield disposed over and extending along sidewalls of the molding compound. The EMI shield contacts the conductive TIV, and the conductive TIV electrically connects the EMI shield to an external connector. The external connector and the EMI shield are disposed on opposing sides of the device die.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 7, 2017
    Inventors: Wei-Yu Chen, Hsien-Wei Chen, An-Jhih Su, Jo-Mei Wang, Tien-Chung Yang
  • Wafer level shielding in multi-stacked fan out packages and methods of forming same
    Patent number: 9659878
    Abstract: An embodiment device package includes a device die, a molding compound surrounding the device die, a conductive through inter-via (TIV) extending through the molding compound, and an electromagnetic interference (EMI) shield disposed over and extending along sidewalls of the molding compound. The EMI shield contacts the conductive TIV, and the conductive TIV electrically connects the EMI shield to an external connector. The external connector and the EMI shield are disposed on opposing sides of the device die.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Hsien-Wei Chen, An-Jhih Su, Jo-Mei Wang, Tien-Chung Yang
  • WAFER LEVEL SHIELDING IN MULTI-STACKED FAN OUT PACKAGES AND METHODS OF FORMING SAME
    Publication number: 20170110413
    Abstract: An embodiment device package includes a device die, a molding compound surrounding the device die, a conductive through inter-via (TIV) extending through the molding compound, and an electromagnetic interference (EMI) shield disposed over and extending along sidewalls of the molding compound. The EMI shield contacts the conductive TIV, and the conductive TIV electrically connects the EMI shield to an external connector. The external connector and the EMI shield are disposed on opposing sides of the device die.
    Type: Application
    Filed: October 20, 2015
    Publication date: April 20, 2017
    Inventors: Wei-Yu Chen, Hsien-Wei Chen, An-Jhih Su, Jo-Mei Wang, Tien-Chung Yang
  • Devices, Packaging Devices, and Methods of Packaging Semiconductor Devices
    Publication number: 20150371947
    Abstract: Devices, packaging devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes a molding material and a plurality of through-vias disposed within the molding material. A dummy through-via and an integrated circuit die are also disposed within the molding material. An interconnect structure is disposed over the molding material, the plurality of through-vias, the dummy through-via, and the integrated circuit die.
    Type: Application
    Filed: March 31, 2015
    Publication date: December 24, 2015
    Inventors: Hsien-Wei Chen, An-Jhih Su, Jo-Mei Wang