Patents by Inventor Jo-won Lee

Jo-won Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10370535
    Abstract: A flame retardant resin composition that can have excellent low smoke properties includes (A) a polycarbonate resin, (B) a silicon impact modifier, and (C) a flame retardant, wherein the (B) silicon impact modifier comprises particles having a core-shell structure, and including about 60 wt % or more of a siloxane polymer, and wherein the (C) flame retardant includes a mixture of magnesium carbonate represented by Formula 1 and magnesium calcium carbonate represented by Formula 2: Mga(CO3)b(OH)2a?2b.cH2O??[Formula 1] wherein a, b and c are as defined in the detailed description; MgxCay(CO3)x+y.mH2O??[Formula 2] wherein x, y and m are as defined in the detailed description.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 6, 2019
    Assignee: Lotte Advanced Materials Co., Ltd.
    Inventor: Jo Won Lee
  • Publication number: 20170349746
    Abstract: A flame retardant resin composition that can have excellent low smoke properties includes (A) a polycarbonate resin, (B) a silicon impact modifier, and (C) a flame retardant, wherein the (B) silicon impact modifier comprises particles having a core-shell structure, and including about 60 wt % or more of a siloxane polymer, and wherein the (C) flame retardant includes a mixture of magnesium carbonate represented by Formula 1 and magnesium calcium carbonate represented by Formula 2: Mga(CO3)b(OH)2a?2b.cH2O ??[Formula 1] wherein a, b and c are as defined in the detailed description; MgxCay(CO3)x+y.mH2O ??[Formula 2] wherein x, y and m are as defined in the detailed description.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 7, 2017
    Inventor: Jo Won LEE
  • Publication number: 20170316949
    Abstract: The present disclosure relates to a method of etching an atomic layer, that is capable of simultaneously removing an upper surface and a side surface of an etch subject material layer by heating with a light source of a lamp when removing the atomic layer, thereby easily reducing the planar size even in the case of patterns in the scale of several nanometers.
    Type: Application
    Filed: April 27, 2017
    Publication date: November 2, 2017
    Applicants: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY, IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Geunyoung YEOM, Kyong Nam KIM, Ki Seok KIM, Mu Kyeom MUN, Jinwoo PARK, Deokhyeon YUN, Jo-Won LEE
  • Patent number: 9790364
    Abstract: A thermoplastic resin composition and a molded article manufactured using the same. The thermoplastic resin composition includes: a polycarbonate resin; a rubber-modified aromatic vinyl graft copolymer; an aromatic vinyl copolymer resin; a phosphorus flame retardant; and inorganic fillers, wherein the rubber-modified aromatic vinyl graft copolymer comprises a first rubber-modified aromatic vinyl graft copolymer comprising a rubber polymer having an average particle diameter (D50) of about 100 nm to about 135 nm and a second rubber-modified aromatic vinyl graft copolymer comprising a rubber polymer having an average particle diameter (D50) of about 250 nm to about 400 nm, and a weight ratio of the first rubber-modified aromatic vinyl graft copolymer to the second rubber-modified aromatic vinyl graft copolymer ranges from about 1:0.1 to about 1:about 10. The thermoplastic resin composition can exhibit excellent properties in terms of fatigue resistance, impact resistance, and flame retardancy.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: October 17, 2017
    Assignee: Lotte Advanced Materials Co., Ltd.
    Inventors: Woo Jin Lee, Jo Won Lee, Hyuk Jin Jeong
  • Publication number: 20170044364
    Abstract: A thermoplastic resin composition and a molded article manufactured using the same. The thermoplastic resin composition includes: a polycarbonate resin; a rubber-modified aromatic vinyl graft copolymer; an aromatic vinyl copolymer resin; a phosphorus flame retardant; and inorganic fillers, wherein the rubber-modified aromatic vinyl graft copolymer comprises a first rubber-modified aromatic vinyl graft copolymer comprising a rubber polymer having an average particle diameter (D50) of about 100 nm to about 135 nm and a second rubber-modified aromatic vinyl graft copolymer comprising a rubber polymer having an average particle diameter (D50) of about 250 nm to about 400 nm, and a weight ratio of the first rubber-modified aromatic vinyl graft copolymer to the second rubber-modified aromatic vinyl graft copolymer ranges from about 1:0.1 to about 1:about 10. The thermoplastic resin composition can exhibit excellent properties in terms of fatigue resistance, impact resistance, and flame retardancy.
    Type: Application
    Filed: August 11, 2016
    Publication date: February 16, 2017
    Inventors: Woo Jin LEE, Jo Won LEE, Hyuk Jin JEONG
  • Publication number: 20150094414
    Abstract: A thermoplastic resin composition includes: a base resin including a polyarylene ether resin and an aromatic vinyl polymer; a flame retardant; and an impact modifier, wherein the impact modifier is a rubber-modified vinyl graft copolymer in which an unsaturated monomer including about 95 wt % to about 99 wt % of an aromatic vinyl compound and about 1 wt % to about 5 wt % of a vinyl cyanide compound is grafted to a rubbery polymer; the base resin and the flame retardant form a continuous phase; and the impact modifier forms a dispersed phase. The thermoplastic resin composition can have excellent properties in terms of impact resistance, flame retardancy, and balance therebetween.
    Type: Application
    Filed: September 26, 2014
    Publication date: April 2, 2015
    Inventors: Jo Won LEE, Dong Min PARK, Seung Shik SHIN, Kyuong Sik CHIN
  • Publication number: 20140187688
    Abstract: A (meth)acrylic copolymer is a copolymer of a monomer mixture including a phosphorus-based (meth)acrylic monomer represented by Formula 1, and a monofunctional unsaturated monomer. The (meth)acrylic copolymer can have improved refractive index, excellent flame resistance, transparency, scratch resistance and/or environment-friendliness: wherein R1 is hydrogen or methyl, R2 is a substituted or unsubstituted C1-C20 hydrocarbon group, R3 and R4 are the same or different and are each independently a substituted or unsubstituted C6-C20 cyclic hydrocarbon group, m is an integer from 1 to 10, and n is an integer from 0 to 5.
    Type: Application
    Filed: June 27, 2013
    Publication date: July 3, 2014
    Inventors: Joo Hyun JANG, Kee Hae KWON, Bo Eun KIM, Yong Hee KANG, Ja Kwan GOO, Man Suk KIM, Il Jin KIM, Kwang Soo PARK, Natarajan Senthilkumar, Jo Won LEE
  • Publication number: 20140184035
    Abstract: Disclosed herein is a television housing and a method of fabricating the same. The television housing includes a stainless steel (SUS) frame and a plastic member adjoining at least one surface of the stainless steel frame. The plastic member includes: a base resin including about 60 wt % to about 95 wt % of (A) a polycarbonate resin and about 5 wt % to about 40 wt % of (B) a rubber-modified aromatic vinyl graft copolymer resin; and about 5 parts by weight to about 25 parts by weight of (C) bondable glass fibers based on about about 100 parts by weight of the base resin including the (A) polycarbonate resin and the (B) rubber-modified aromatic vinyl graft copolymer resin, and has a tensile strength from about 70 MPa to about 130 MPa at about 23° C. The plastic member employs the bondable glass fibers, and thus can prevent whitening due to an ejector pin upon release at high temperature.
    Type: Application
    Filed: December 18, 2013
    Publication date: July 3, 2014
    Applicant: Cheil Industries Inc.
    Inventors: Jo Won LEE, Kyuong Sik CHIN, Ji Yea KIM, Sang Ki PARK, Seung Shik SHIN
  • Patent number: 8237214
    Abstract: A non-volatile memory device including a metal-insulator transition (MIT) material is provided. The non-volatile memory device includes a gate stack having a tunneling layer, a charge trap layer, a blocking layer and a gate electrode formed on a substrate, wherein at least one of the tunneling layer and the blocking layer is formed of an MIT (metal-insulator transition) material.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: August 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan-jun Park, Jo-won Lee, Sang-hun Jeon, Chung-woo Kim
  • Patent number: 8139387
    Abstract: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: March 20, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-dong Park, Jo-won Lee, Chung-woo Kim, Eun-hong Lee, Sun-ae Seo, Woo-joo Kim, Hee-soon Chae, Soo-doo Chae, I-hun Song
  • Publication number: 20100296347
    Abstract: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.
    Type: Application
    Filed: May 14, 2010
    Publication date: November 25, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoon-dong Park, Jo-won Lee, Chung-woo Kim, Eun-hong Lee, Sun-ae Seo, Woo-joo Kim, Hee-soon Chae, Soo-doo Chae, I-hun Song
  • Patent number: 7759196
    Abstract: A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: July 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-doo Chae, Moon-kyung Kim, Jo-won Lee, Chung-woo Kim
  • Patent number: 7719871
    Abstract: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: May 18, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-dong Park, Jo-won Lee, Chung-woo Kim, Eun-hong Lee, Sun-ae Seo, Woo-joo Kim, Hee-soon Chae, Soo-doo Chae, I-hun Song
  • Publication number: 20090010058
    Abstract: A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.
    Type: Application
    Filed: September 12, 2008
    Publication date: January 8, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-doo CHAE, Moon-kyung Kim, Jo-won Lee, Chung-woo Kim
  • Patent number: 7432554
    Abstract: A complementary metal oxide semiconductor (CMOS) thin film transistor including a common gate, a logic device including the CMOS thin film transistor, and a method of manufacturing the CMOS thin film transistor are provided. In one embodiment, the CMOS thin film transistor includes a base substrate and a semiconductor layer formed on the base substrate. A PMOS transistor and an NMOS transistor are formed on a single semiconductor layer to intersect each other, and a common gate is formed on the intersection area. In addition, a Schottky barrier inducing material layer is formed on a source and a drain of the PMOS transistor.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: October 7, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-Kyung Kim, Jo-Won Lee, Yoon-Dong Park, Chung-Woo Kim
  • Publication number: 20080212376
    Abstract: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.
    Type: Application
    Filed: February 4, 2008
    Publication date: September 4, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoon-dong Park, Jo-won Lee, Chung-woo Kim, Eun-hong Lee, Sun-ae Seo, Woo-joo Kim, Hee-soon Chae, Soo-doo Chae, I-hun Song
  • Publication number: 20080157186
    Abstract: A non-volatile memory device including a metal-insulator transition (MIT) material is provided. The non-volatile memory device includes a gate stack having a tunneling layer, a charge trap layer, a blocking layer and a gate electrode formed on a substrate, wherein at least one of the tunneling layer and the blocking layer is formed of an MIT (metal-insulator transition) material.
    Type: Application
    Filed: October 31, 2007
    Publication date: July 3, 2008
    Inventors: Wan-jun Park, Jo-won Lee, Sang-hun Jeon, Chung-woo Kim
  • Patent number: 7374991
    Abstract: In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region, and a channel region, a first side gate stack formed at a first side of the channel region, and a second side gate stack formed at a second side of the channel region opposite the first side of the channel region. In the SONOS memory device, at least two bits of data may be stored in each SONOS memory device, thereby allowing the integration density of the semiconductor memory device to be increased without increasing an area thereof.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: May 20, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-il Ryu, Jo-won Lee, Se-wook Yoon, Chung-woo Kim
  • Patent number: 7345898
    Abstract: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: March 18, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-dong Park, Jo-won Lee, Chung-woo Kim, Eun-hong Lee, Sun-ae Seo, Woo-joo Kim, Hee-soon Chae, Soo-doo Chae, I-hun Song
  • Publication number: 20070138541
    Abstract: A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes. This erasing improves erasing speed, thereby improving performance of the SONOS memory device.
    Type: Application
    Filed: February 5, 2007
    Publication date: June 21, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-doo Chae, Chung-woo Kim, Jo-won Lee, Moon-kyung Kim