Abstract: An auto-zero amplifier is disclosed, having an amplifying circuit, a switch, and a difference signal generating circuit. The amplifying circuit receives a first input signal for generating a first output signal, and receives a second input signal for generating a second output signal. The switch is coupled between the amplifying circuit and a capacitor. The switch is conducted for charging or discharging the capacitor to a voltage with the first output signal, and the switch is not conducted for keeping the capacitor at the voltage. The difference signal generating circuit is coupled with the amplifying circuit and the capacitor for generating a difference signal of the first output signal and the second output signal, a multiple of the difference signal, a part of the difference signal, and/or a digital output value for the difference signal.

Abstract: The present invention discloses a switching regulator including: a power stage having an upper gate device and a lower gate device coupled with each other, for converting an input voltage to an output voltage and generating a phase voltage at a node between the upper gate device and the lower gate device; and a control circuit including: a switch operation circuit controlling the power stage, the switch operation circuit generating a test signal turning on the upper gate device for a period of time and then turning it off; and a comparator for generating a ready signal indicating that the input voltage is ready according to comparison between the phase voltage and a reference voltage after the upper gate device is turned off.

Abstract: A zero-crossing detection circuit and a commutation device using the zero-crossing detection circuit are provided. The zero-crossing detection circuit is adapted into a three-phase brushless DC (direct current) motor with first to third coils. One terminal of each of the first to third coils is electrically coupled together with each other. The detection circuit comprises a first selection circuit, a second selection circuit and a comparator. The first selection circuit and the second selection circuit are both electrically coupled to another terminals of the first to third coils, to obtain first to third terminal voltages, and output one of the first to third terminal voltages according to a selection signal. The comparator is configured for comparing an output of the first selection circuit and an output of the second selection circuit, to output a comparing result.

Abstract: The present invention discloses a voltage mode switching regulator with improved light load efficiency and mode transition characteristic, and a control circuit and a control method therefor. The switching regulator can switch between a pulse width modulation (PWM) mode and a pulse skipping mode. The control method for the switching regulator comprises: comparing a feedback signal relating to an output voltage with a reference signal, to generate an error amplification signal; generating a duty signal according to the error amplification signal and a ramp signal, to control the switching regulator; setting a threshold level of the error amplification signal and a threshold level of the pulse skipping mode according to the error amplification signal in a stable status; and when the error amplification signal is close or equal to the threshold level of the pulse skipping mode, generating a pulse skip signal to enter the pulse skipping mode.

Abstract: A first switch is switched to short a multi-functional pin of an integrated circuit to a ground terminal or let a current supplied to the multi-functional pin to flow to a second switch connected to the multi-functional pin. Before the integrated circuit is ready, the second switch is closed circuit and is detected its current to determine a first signal to enable or disable the integrated circuit. After the integrated circuit is ready, the second switch is open circuit, the voltage at the multi-functional pin is detected to determine a second signal to enable or disable the integrated circuit, and when the voltage at the multi-functional pin is higher than a threshold, a power good signal is triggered.

Abstract: The present invention discloses a switching regulator and control method thereof, and a method for determining On-time in switching regulator. The switching regulator comprises: a power switch circuit including at least one power transistor switch which operates to convert an input voltage to an output voltage; a PWM generation circuit for generating a duty signal in a normal operation mode according to a feedback signal relating to the output voltage; a pulse skipping circuit for determining On-time in a pulse skipping mode according to a node with non-constant voltage level, the node being connected with the power transistor switch; and a driver circuit for driving the at least one power transistor switch according to one of the outputs from the PWM generation circuit and the pulse skipping circuit.

Abstract: A parameter setting circuit and method for an integrated circuit apply a pulse current to a pin of the integrated circuit during a programming mode of the integrated circuit, and then extract the difference between the voltage on the pin and the DC component of the voltage on the pin to determine a setting signal for parameter setting to an internal circuit of the integrated circuit. By this way, an input pin, an output pin or an input/output pin of the integrated circuit may be used as the pin implementing the parameter setting function.

Abstract: For a system to avoid abnormal operation caused by a shorted parameter setting pin of an integrated circuit, a protection apparatus and method apply a buffered reference voltage to the parameter setting pin to define an internal parameter of the integrated circuit by the buffered reference voltage and an external element connected to the parameter setting pin, and detect the rapid variation of the internal parameter to trigger a shutdown signal or slow down the speed of the variation of the internal parameter reflected to an adjustable signal of the integrated circuit.

Abstract: A ramp generator is provided to provide a multi-slope ramp signal for a PWM power converter. The ramp generator determines the slope turning points for the multi-slope ramp signal according to the error signal of the PWM power converter and thereby improve the transient response of the PWM power converter. Preferably, the slope turning point of the multi-slope ramp signal varies with the average of the error signal and is thus adaptive to the error signal and thereby the load condition.

Abstract: The present invention discloses a switching regulator and control method thereof, and a method for determining On-time in switching regulator. The switching regulator comprises: a power switch circuit including at least one power transistor switch which operates to convert an input voltage to an output voltage; a PWM generation circuit for generating a duty signal in a normal operation mode according to a feedback signal relating to the output voltage; a pulse skipping circuit for determining On-time in a pulse skipping mode according to a node with non-constant voltage level, the node being connected with the power transistor switch; and a driver circuit for driving the at least one power transistor switch according to one of the outputs from the PWM generation circuit and the pulse skipping circuit.

Abstract: The present invention discloses a voltage mode switching regulator with improved light load efficiency and mode transition characteristic, and a control circuit and a control method therefor. The switching regulator can switch between a pulse width modulation (PWM) mode and a pulse skipping mode. The control method for the switching regulator comprises: comparing a feedback signal relating to an output voltage with a reference signal, to generate an error amplification signal; generating a duty signal according to the error amplification signal and a ramp signal, to control the switching regulator; setting a threshold level of the error amplification signal and a threshold level of the pulse skipping mode according to the error amplification signal in a stable status; and when the error amplification signal is close or equal to the threshold level of the pulse skipping mode, generating a pulse skip signal to enter the pulse skipping mode.

Abstract: A ramp generator is provided to provide a multi-slope ramp signal for a PWM power converter. The ramp generator determines the slope turning points for the multi-slope ramp signal according to the error signal of the PWM power converter and thereby improve the transient response of the PWM power converter. Preferably, the slope turning point of the multi-slope ramp signal varies with the average of the error signal and is thus adaptive to the error signal and thereby the load condition.

Abstract: Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells.

Abstract: A non-volatile memory device with a page buffer having dual registers includes a memory cell array, a selector circuit and a page buffer circuit, the selector circuit being coupled to an exterior data line, the page buffer circuit including a first register and a second register being coupled between the memory cell array and the selector circuit, and the first register and second register being commonly coupled through a sense node. The first and second registers alternately write data to the memory cell array for programming. As one of the first and second registers performs programming, the other register stores data from the data line concurrently. In other words, the second register stores data from the data line when the first register is in programming, whereas the first register stores data from the data line when the second register is in programming.

Abstract: Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells.

Abstract: A multi-shifting shift register is adapted for outputting a selected address signal to a memory unit, and includes a control circuit for outputting a number (i) of shift signals and a timing pulse signal. One of the shift signals is at an enabled state and the other ones of the shift signals are at a disabled state during each cycle of the timing pulse signal. A multi-shifting circuit includes a number (N), which is larger than the number (i), of cascaded register units, each of which has a flip-flop that has an input end, and an output end for generating an address signal, and a selector that has the number (i) of select inputs for receiving the number (i) of the shift signals respectively from the control circuit, the number (i) of address signal inputs, and an output. The output end of the flip-flop is connected to a first one of the address signal inputs of the selector.

Abstract: A memory device includes a global decoder circuit and two memory cell array devices, each of which is disposed adjacent to a respective one of opposing first and second sides of the global decoder circuit, and has global word lines coupled to the global decoder circuit. Each of two data input buffers is disposed at a third side of the global decoder circuit adjacent to a respective one of the memory cell arrays, and is coupled to the respective one of the memory cell arrays. A write control circuit is coupled to and is disposed adjacent to the third side of the global decoder circuit. A write clock buffer is disposed adjacent to the third side of the global decoder circuit, and is coupled to the data input buffers. A read control circuit is coupled to and is disposed adjacent to a fourth side of the global decoder circuit. Each of two multiplexer sets is coupled to bit lines of a respective one of the memory cell array devices.