Abstract: An enhanced dual in line memory module (DIMM) connector includes internal conductive paths that provide access to signaling on standard conductive paths to an industry standard DIMM. The internal conductive paths are coupled in series or in parallel with the standard conductive paths through the connector. Interposer circuitry, such as control circuitry and or supplemental memory circuitry, may be incorporated on or within the connector. The interposer circuitry may include field effect transistor (FET) switching circuitry configured to selectively decouple a defective dynamic random memory (DRAM) on a DIMM from a conductive path to a memory controller and couple a substitute DRAM to the conductive paths in its place.

Abstract: Reducing system downtime during memory subsystem maintenance in a computer processing system is disclosed. In some aspects, a computer processing system comprises a computer processor communicatively coupled to a plurality of memory sockets, each of which interfaces with a memory module and includes a gate control. The computer processor is further communicatively coupled to a dedicated non-volatile storage device. Upon detection of a memory health condition requiring replacement of a memory module, access to the memory module is blocked, and data is transferred from the memory module to the dedicated non-volatile storage device. A memory address range of the memory module is then remapped to the dedicated non-volatile storage device, such that subsequent memory access requests to the memory module are rerouted to the dedicated non-volatile storage device. The memory socket of the memory module is then gated, allowing maintenance to be performed while maintaining system availability.

Abstract: An enhanced dual in line memory module (DIMM) connector includes internal conductive paths that provide access to signaling on standard conductive paths to an industry standard DIMM. The internal conductive paths are coupled in series or in parallel with the standard conductive paths through the connector. Interposer circuitry, such as control circuitry and or supplemental memory circuitry, may be incorporated on or within the connector. The interposer circuitry may include field effect transistor (FET) switching circuitry configured to selectively decouple a defective dynamic random memory (DRAM) on a DIMM from a conductive path to a memory controller and couple a substitute DRAM to the conductive paths in its place.