Abstract: A semiconductor device structure includes a semiconductor substrate with an active region provided therein, a gate structure, a dummy gate structure and two contact regions provided in the active region for forming source and drain regions. The gate structure and the dummy gate structure are formed on the semiconductor substrate so as to partially overlie the active region, and one of the contact regions is located at one side of the dummy gate structure. The semiconductor device structure includes a contact structure contacting one of the contact regions and the dummy gate for connecting this contact region and the dummy gate to one of a Vdd rail and a Vss rail. The active region has an extension portion protruding laterally away from the active region relative to the other contact region, where the contact structure is located over the extension portion.

Abstract: A semiconductor device structure includes a semiconductor substrate with an active region provided therein, a gate structure, a dummy gate structure and two contact regions provided in the active region for forming source and drain regions. The gate structure and the dummy gate structure are formed on the semiconductor substrate so as to partially overlie the active region, and one of the contact regions is located at one side of the dummy gate structure. The semiconductor device structure includes a contact structure contacting one of the contact regions and the dummy gate for connecting this contact region and the dummy gate to one of a Vdd rail and a Vss rail. The active region has an extension portion protruding laterally away from the active region relative to the other contact region, where the contact structure is located over the extension portion.

Abstract: A two-dimensional light-section method for measuring the profile geometry of cylindrical bodies is disclosed. A fan-shaped laser line forming a light-section line on the surface of the body is imaged with at least one laser, and the laser radiation reflected from the surface of the body is captured by at least one area imaging camera, wherein the laser and the camera are arranged at a triangulation angle in a normal plane aligned with the cylinder axis. The profile geometry is then measured by pivoting the laser out of the normal plane about the cylinder axis. The angle with respect to the normal plane is selected such that the optical axis of the area imaging camera with respect to the surface of the cylinder is located within the glancing angle range of the reflected beams.

Abstract: A two-dimensional light-section method for measuring the profile geometry of cylindrical bodies is disclosed. A fan-shaped laser line forming a light-section line on the surface of the body is imaged with at least one laser, and the laser radiation reflected from the surface of the body is captured by at least one area imaging camera, wherein the laser and the camera are arranged at a triangulation angle in a normal plane aligned with the cylinder axis. The profile geometry is then measured by pivoting the laser out of the normal plane about the cylinder axis. The angle with respect to the normal plane is selected such that the optical axis of the area imaging camera with respect to the surface of the cylinder is located within the glancing angle range of the reflected beams.

Abstract: A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures are defined by lithography processes using photomasks. At least one of the photomasks includes both openings in a first region for supporting the definition of the first structures and openings in a second region for supporting the definition of the second structures.

Abstract: A memory device having an array portion including memory cells, and a peripheral portion including conductive lines is disclosed. In one embodiment, portions of the conductive lines adjoin a surface of a semiconductor carrier.

Abstract: A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures are defined by lithography processes using photomasks. At least one of the photomasks includes both openings in a first region for supporting the definition of the first structures and openings in a second region for supporting the definition of the second structures.

Abstract: A memory device having an array portion including memory cells, and a peripheral portion including conductive lines is disclosed. In one embodiment, portions of the conductive lines adjoin a surface of a semiconductor carrier.

Abstract: A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.

Abstract: A non-volatile semiconductor memory (30) comprising a semiconductor substrate (1) and a plurality of memory cells (19) and methods for manufacturing such a memory is provided. Each memory cell (19) comprises a charge-trapping element (5), a gate stack (20), nitride spacers (10) and electrically insulating elements (21). The charge-trapping element (5) is arranged on the semiconductor substrate (1) and comprises a nitride layer (3) sandwiched between a bottom oxide layer (2) and a top oxide layer (4), the charge-trapping element (5) having two lateral sidewalls (24) opposed to one another. The gate stack (20) is arranged on top of the charge-trapping element (5), the gate stack having two lateral sidewalls (25) opposing one another. The electrically insulating elements (21) are disposed at opposing sidewalls (24) of the charge-trapping element (5) and cover the sidewalls (24) of the charge-trapping element (5).

Abstract: A trench (2) is fabricated in a silicon body (1). The walls (4) of the trench are provided with a nitrogen implantation (6). An oxide layer between the source/drain regions (5) and a word line applied on the top side grows to a greater thickness than a lower oxide layer of an ONO storage layer fabricated as gate dielectric at the trench wall. Instead of the nitrogen implantation into the trench walls, it is possible to fabricate a metal silicide layer on the top sides of the source/drain regions in order to accelerate the oxide growth there.

Abstract: In the method, trenches (9) are etched and, in between, bit lines (8) are in each case arranged on doped source drain/regions (3). Dopant is introduced into the bottoms of the trenches (9) in order to form doped regions (23), in order to electrically modify the channel regions. Storage layers are applied and gate electrodes (2) are arranged at the trench walls. The semiconductor material at the bottoms of the trenches is etched away between the word lines (18/19) to an extent such that the doped regions (23) are removed there to such a large extent that a crosstalk between adjacent memory cells along the trenches is reduced.

Abstract: In a memory cell, in a trench, a layer sequence comprising a first oxide layer, a nitride layer provided on the first oxide layer, and a second oxide layer, facing the gate electrode, and provided at the lateral trench walls, while the nitride layer is absent in a curved region of the trench bottom. In an alternative configuration, in each case at least one step is formed at the lateral walls of the trench, preferably below the source region or the drain region, respectively.

Abstract: An electrically conductive bit line layer is applied and patterned into portions arranged parallel to one another before the trench is etched into the semiconductor material, in which case, after the patterning of the bit line layer (3, 4) and before the etching of the trench, an implantation is introduced for the purpose of defining the position of the junctions, or, after the implantation of the n+-type well (19) for the source/drain regions, the bit line layer (3, 4) is patterned using an etching stop layer (2) arranged on the semiconductor body (1).

Abstract: A semiconductor product (1) includes a plurality of wordlines extending along a first lateral direction (x) along a substrate surface (22) and also includes contact structures (3) as well as filling structures (4) therebetween. Along the first direction (x) the contact structures (3) and the filling structures (4) are arranged in alternating order between two respective wordlines. Each contact structure (3) serves to connect two active areas (23) separated by one respective trench isolation filling (24) to a respective bitline (14). Accordingly, the width of the first contact structures (3) is much larger than the width of the bitlines (14) along the first direction (x). According to embodiments of the invention, tapered upper portions (9) of the contact structures (3) are shaped, the upper portions (9) having a width being significantly smaller than the width of the contact structures (3) along the first direction (x).

Abstract: A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.

Abstract: A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.

Abstract: The surfaces of wordline stacks and intermediate areas of a main substrate surface are covered with an oxynitride liner. Either sidewall spacers of BPSG are formed or a further liner of nitride is deposited and spacers of oxide are formed. These spacers are used in a peripheral area of addressing circuitry to implant doped source/drain regions. The oxynitride reduces the stress between the nitride and the semiconductor material and prevents charge carriers from penetrating out of a memory layer of nitride into the liner.

Abstract: A method and device for measuring the wall thickness of a pipe in a pipe-rolling mill wherein a Fabry-Pérot interfero-meter has its mirror spacing set by providing an input to a linear activity for one of the mirrors from a controller receiving an input from a photodiode at the output side of the interferometer. A second control circuit regulates the amplification of that photodiode with at least one parameter derived from the rolling system, for example, the input optical signal to the interferometer or a disturbance value representing for example the temperature of the rolled product and obtained through an optical pyrometer. The incoming optical signal may be tapped to another photodiode also with a variable amplification amplifier and both amplifiers may be controlled by a second controller.

Abstract: A non-volatile semiconductor memory (30) comprising a semiconductor substrate (1) and a plurality of memory cells (19) and methods for manufacturing such a memory is provided. Each memory cell (19) comprises a charge-trapping element (5), a gate stack (20), nitride spacers (10) and electrically insulating elements (21). The charge-trapping element (5) is arranged on the semiconductor substrate (1) and comprises a nitride layer (3) sandwiched between a bottom oxide layer (2) and a top oxide layer (4), the charge-trapping element (5) having two lateral sidewalls (24) opposed to one another. The gate stack (20) is arranged on top of the charge-trappinig element (5), the gate stack having two lateral sidewalls (25) opposing one another. The electrically insulating elements (21) are disposed at opposing sidewalls (24) of the charge-trapping element (5) and cover the sidewalls (24) of the charge-trapping element (5).