Patents by Inventor Joachim Fader
Joachim Fader has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230292047Abstract: An audio configuration system receives an analyzes ultrawideband radio return signals resulting from one or more pulsed UWB probe signals. The system receives the UWB return signals. The UWB return signals are used to determine a spatial orientation of one or more objects (e.g., one or more seats in a passenger cabin of a vehicle). The system causes audio circuitry to output audio signals according to audio configuration parameters determined by the spatial orientation of the object or objects.Type: ApplicationFiled: March 14, 2022Publication date: September 14, 2023Inventors: Surendra Guntur, Joachim Fader, Wolfgang Küchler
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Patent number: 11399084Abstract: A MIPI CSI-2/D-PHY receiving device is configured to handle being hot plugged to MIPI CSI-2/D-PHY transmitting device. During a hot plugging event, the MIPI CSI-2/D-PHY receiving device has not been initialized by receipt from the MIPI CSI-2/D-PHY transmitting device of a Stop State signal of duration TINIT. Though the MIPI CSI-2/D-PHY transmitting device is already transmitting data associated with a partial frame, the MIPI CSI-2/D-PHY receiving device will not enter into an error or unknown state, and will ignore line start/end and frame end events and drop the data packets associated with the partial frame until a frame start event corresponding to a full frame is received from the MIPI CSI-2/D-PHY transmitting device.Type: GrantFiled: May 12, 2020Date of Patent: July 26, 2022Assignee: NXP USA, Inc.Inventors: Joachim Fader, Naveen Kumar Jain, Shreya Singh, Thomas John Rodriguez, Shivali Jain
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Publication number: 20210360090Abstract: A MIPI CSI-2/D-PHY receiving device is configured to handle being hot plugged to MIPI CSI-2/D-PHY transmitting device. During a hot plugging event, the MIPI CSI-2/D-PHY receiving device has not been initialized by receipt from the MIPI CSI-2/D-PHY transmitting device of a Stop State signal of duration TINIT. Though the MIPI CSI-2/D-PHY transmitting device is already transmitting data associated with a partial frame, the MIPI CSI-2/D-PHY receiving device will not enter into an error or unknown state, and will ignore line start/end and frame end events and drop the data packets associated with the partial frame until a frame start event corresponding to a full frame is received from the MIPI CSI-2/D-PHY transmitting device.Type: ApplicationFiled: May 12, 2020Publication date: November 18, 2021Applicant: NXP USA, Inc.Inventors: Joachim Fader, Naveen Kumar Jain, Shreya Singh, Thomas John Rodriguez, Shivali Jain
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Patent number: 10862830Abstract: A system and method for real-time data transfer on a system-on-chip (SoC) allows MIPI-CSI (camera serial interface) data received on a first interface to be output on another MIPI-CSI interface without using system memory or delaying the loopback path. The system includes a CSI receiver, a loopback buffer, and a CSI transmitter. The loopback buffer is used for the data transfer between the CSI receiver and the CSI transmitter. The CSI transmitter receives a payload included in a data packet from the CSI receiver by way of the loopback buffer. The CSI receiver communicates a packet header of the data packet to the CSI transmitter. The CSI transmitter reads the payload from the loopback buffer based on the packet header and at least one of a buffer threshold capacity and payload size.Type: GrantFiled: December 17, 2018Date of Patent: December 8, 2020Assignee: NXP USA, INC.Inventors: Naveen Kumar Jain, Joachim Fader, Shreya Singh, Nishant Jain, Anshul Goel
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Publication number: 20200195589Abstract: A system and method for real-time data transfer on a system-on-chip (SoC) allows MIPI-CSI (camera serial interface) data received on a first interface to be output on another MIPI-CSI interface without using system memory or delaying the loopback path. The system includes a CSI receiver, a loopback buffer, and a CSI transmitter. The loopback buffer is used for the data transfer between the CSI receiver and the CSI transmitter. The CSI transmitter receives a payload included in a data packet from the CSI receiver by way of the loopback buffer. The CSI receiver communicates a packet header of the data packet to the CSI transmitter. The CSI transmitter reads the payload from the loopback buffer based on the packet header and at least one of a buffer threshold capacity and payload size.Type: ApplicationFiled: December 17, 2018Publication date: June 18, 2020Inventors: Naveen Kumar Jain, Joachim Fader, Shreya Singh, Nishant Jain, Anshul Goel
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Patent number: 10540284Abstract: A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system.Type: GrantFiled: July 29, 2014Date of Patent: January 21, 2020Assignee: NXP USA, Inc.Inventors: Dirk Wendel, Oliver Bibel, Joachim Fader, Wilhard Christophorus Von Wendorff
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Patent number: 10311241Abstract: A system on a chip (SoC) and method of operation are described. A data processor has a processor data word size of p×octets and is configured to handle data items having a data item size which is a non-integer multiple of the processor data word size. A memory controller is configured to write or read data items to a memory as multiples of m×octets. Data can be sent between the data processor and the memory controller on a bus. A data protection code generator is configured to generate a data protection code for a data item generated by the data processor before transmitting the data item and the data protection code over the bus to the memory controller which writes at least one octet including at least a portion of the data item and at least a portion of the data protection code to an address. A data protection code checker is configured to receive a read data protection code and a read data item and to check the read data item for an error using the read data protection code.Type: GrantFiled: September 12, 2017Date of Patent: June 4, 2019Assignee: NXP USA, Inc.Inventors: Joachim Fader, Robert Krutsch, Dirk Wendel
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Patent number: 10241941Abstract: Methods and systems are disclosed for asymmetric memory access to memory banks within integrated circuit (IC) systems. Disclosed embodiments include a memory and a memory controller within an integrated circuit. The memory includes a number of different memory banks, and the memory controller includes a number of different access ports coupled to the memory banks. The memory controller is also configured to provide asymmetric memory access for access requests to memory banks based upon access ports used for memory access requests. Additional disclosed embodiments further use asymmetric access times or asymmetric access bandwidths to provide this asymmetric access to memory banks within system memories for integrated circuit (IC) systems. By providing asymmetric access times or bandwidths for multiple access ports within a memory controller to multiple different memory banks within a system memory, overall access latency or system cost is reduced for the IC systems.Type: GrantFiled: June 29, 2015Date of Patent: March 26, 2019Assignee: NXP USA, Inc.Inventors: Joachim Fader, Stephan M. Herrmann, Amit Jindal, Nitin Singh
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Patent number: 10210088Abstract: The present application relates to a cache invalidation unit for a computing system having a processor unit, CPU, with a cache memory, a main memory and at least one an alternate bus master unit. The CPU, the main memory and the at least one an alternate bus master unit are coupled via an interconnect for data communications between them. The cache invalidation unit generates one or more invalidation requests to the cache memory in response to the alternate bus master unit writing data to the main memory. The cache invalidation unit comprises a page address generator unit to generate page addresses relating to at least one address range and an invalidation request generator unit to generate an invalidation request for each page address. The one or more generated invalidation requests are transmitted by the cache invalidation unit via to the cache memory of the CPU.Type: GrantFiled: December 28, 2015Date of Patent: February 19, 2019Assignee: NXP USA, Inc.Inventors: Ray Charles Marshall, Nancy Hing-Che Amedeo, Joachim Fader
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Patent number: 10049052Abstract: A device has a cache memory for temporarily storing contents of a buffer memory. The device has a mirror unit coupled between the cache memory and the buffer memory. The mirror unit is arranged for providing at least two buffer mirrors at respective different buffer mirror address ranges in the main address range by adapting the memory addressing. Due to the virtual mirrors data on a respective address in any of the respective different buffer mirror address ranges is the data of the buffer memory at a corresponding address in the buffer address range. The device enables processing of a subsequent set of data in the buffer memory via the cache memory without invalidating the cache by switching to a different buffer mirror.Type: GrantFiled: October 27, 2014Date of Patent: August 14, 2018Assignee: NXP USA, Inc.Inventors: Ray Charles Marshall, Joachim Fader, Stephan Herrmann
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Publication number: 20180157848Abstract: A system on a chip (SoC) and method of operation are described. A data processor has a processor data word size of p×octets and is configured to handle data items having a data item size which is a non-integer multiple of the processor data word size. A memory controller is configured to write or read data items to a memory as multiples of m×octets. Data can be sent between the data processor and the memory controller on a bus. A data protection code generator is configured to generate a data protection code for a data item generated by the data processor before transmitting the data item and the data protection code over the bus to the memory controller which writes at least one octet including at least a portion of the data item and at least a portion of the data protection code to an address. A data protection code checker is configured to receive a read data protection code and a read data item and to check the read data item for an error using the read data protection code.Type: ApplicationFiled: September 12, 2017Publication date: June 7, 2018Inventors: Joachim Fader, Robert Krutsch, Dirk Wendel
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Patent number: 9940186Abstract: A memory controller includes a transaction interface arranged to be coupled to a transaction interconnect to receive a write transaction comprising write data, a mode controller arranged to obtain context information and to select a data protection scheme out of a plurality of data protection schemes based on the obtained context information, at least one data protection module to apply the selected data protection scheme by generating one or more protection code sequences from at least the write data in accordance with the selected data protection scheme, and a physical memory interface coupled to at least one memory device to store the write data and the one or more protection code sequences in the at least one memory device.Type: GrantFiled: December 22, 2015Date of Patent: April 10, 2018Assignee: NXP USA, Inc.Inventors: Joachim Fader, Ray Charles Marshall, Dirk Wendel
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Patent number: 9826252Abstract: A method for detecting a freeze-frame condition comprises receiving a sequence of images from at least one digital device; selectively encoding a first subset of the sequence of images using a first coding scheme that causes an adjustment to an image characteristic of the selected images being encoded; selectively encoding a second subset of the sequence of images using a second coding scheme; storing the first encoded subset and second encoded subset; retrieving the stored first encoded subset and second encoded subset; selectively decoding the first subset of the selected images using the first coding scheme and selectively decoding the second subset of the selected images using the second coding scheme to re-create the sequence of images. A freeze-frame condition in the re-created sequence of images is identifiable based on a plurality of decoded images being different with respect to the image characteristic across multiple decoded image frames.Type: GrantFiled: July 29, 2014Date of Patent: November 21, 2017Assignee: NXP USA, Inc.Inventors: Dirk Wendel, Joachim Fader, Stephan Herrmann, Wilhard Christophorus Von Wendorff
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Patent number: 9823959Abstract: A microcontroller unit having a functional state, a reset state, and one or more assertable fault sources is described. Each fault source has its own fault source assertion count and its own fault source assertion limit; the MCU is arranged to perform the following sequence of operations in a cyclic manner: if one or more of the fault sources are asserted, pass from the functional state to the reset state and increase the respective fault source assertion counts by one increment; if one or more of the fault source assertion counts exceeds the respective fault source assertion limit, disable the respective fault source; and pass from the reset state to the functional state. A method of operating an MCU is also disclosed.Type: GrantFiled: May 13, 2013Date of Patent: November 21, 2017Assignee: NXP USA, Inc.Inventors: Vladimir Litovtchenko, Joachim Fader, Harald Luepken
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Publication number: 20170185519Abstract: The present application relates to a cache invalidation unit for a computing system having a processor unit, CPU, with a cache memory, a main memory and at least one an alternate bus master unit. The CPU, the main memory and the at least one an alternate bus master unit are coupled via an interconnect for data communications between them. The cache invalidation unit generates one or more invalidation requests to the cache memory in response to the alternate bus master unit writing data to the main memory. The cache invalidation unit comprises a page address generator unit to generate page addresses relating to at least one address range and an invalidation request generator unit to generate an invalidation request for each page address. The one or more generated invalidation requests are transmitted by the cache invalidation unit via to the cache memory of the CPU.Type: ApplicationFiled: December 28, 2015Publication date: June 29, 2017Inventors: Ray Charles Marshall, Nancy Hing-Che Amedeo, Joachim Fader
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Publication number: 20170177432Abstract: The present application relates to a memory controller and a method of operating thereof. The memory controller comprises a transaction interface arranged to be coupled to a transaction interconnect to receive a write transaction comprising write data; a mode controller arranged to obtain context information and to select a data protection scheme out of a plurality of data protection schemes based on the obtained context information; at least one data protection module to apply the selected data protection scheme by generating one or more protection code sequences from at least the write data in accordance with the selected data protection scheme; and a physical memory interface coupled to at least one memory device to store the write data and the one or more protection code sequences in the at least one memory device.Type: ApplicationFiled: December 22, 2015Publication date: June 22, 2017Inventors: Joachim Fader, Ray Charles Marshall, Dirk Wendel
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Publication number: 20160378695Abstract: Methods and systems are disclosed for asymmetric memory access to memory banks within integrated circuit (IC) systems. Disclosed embodiments include a memory and a memory controller within an integrated circuit. The memory includes a number of different memory banks, and the memory controller includes a number of different access ports coupled to the memory banks. The memory controller is also configured to provide asymmetric memory access for access requests to memory banks based upon access ports used for memory access requests. Additional disclosed embodiments further use asymmetric access times or asymmetric access bandwidths to provide this asymmetric access to memory banks within system memories for integrated circuit (IC) systems. By providing asymmetric access times or bandwidths for multiple access ports within a memory controller to multiple different memory banks within a system memory, overall access latency or system cost is reduced for the IC systems.Type: ApplicationFiled: June 29, 2015Publication date: December 29, 2016Inventors: Joachim Fader, Stephan M. Herrmann, Amit Jindal, Nitin Singh
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Publication number: 20160124800Abstract: A microcontroller unit (MCU) having a functional state, a reset state, and one or more assertable fault sources is described. Each fault source has its own fault source assertion count and its own fault source assertion limit; the MCU is arranged to perform the following sequence of operations in a cyclic manner: if one or more of the fault sources are asserted, pass from the functional state to the reset state and increase the respective fault source assertion counts by one increment; if one or more of the fault source assertion counts exceeds the respective fault source assertion limit, disable the respective fault source; and pass from the reset state to the functional state. A method of operating an MCU is also disclosed.Type: ApplicationFiled: May 13, 2013Publication date: May 5, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Vladimir Litovtchenko, Joachim Fader, Harald Luepken
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Publication number: 20160117255Abstract: A device has a cache memory for temporarily storing contents of a buffer memory. The device has a mirror unit coupled between the cache memory and the buffer memory. The mirror unit is arranged for providing at least two buffer mirrors at respective different buffer mirror address ranges in the main address range by adapting the memory addressing. Due to the virtual mirrors data on a respective address in any of the respective different buffer mirror address ranges is the data of the buffer memory at a corresponding address in the buffer address range. The device enables processing of a subsequent set of data in the buffer memory via the cache memory without invalidating the cache by switching to a different buffer mirror.Type: ApplicationFiled: October 27, 2014Publication date: April 28, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: RAY CHARLES MARSHALL, JOACHIM FADER, STEPHAN HERRMANN
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Publication number: 20160034398Abstract: A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system.Type: ApplicationFiled: July 29, 2014Publication date: February 4, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: DIRK WENDEL, OLIVER BIBEL, JOACHIM FADER, WILHARD CHRISTOPHORUS VON WENDORFF