Abstract: An example embodiment may involve identifying local traces of related events within a plurality of event data repositories, wherein each of the event data repositories is respectively associated with a software application; using a clustering model, assigning the local traces into clusters; determining positive rules that define when pairs of the local traces are linked to a common global trace, and negative rules that define when the pairs are linked to different global traces; linking the pairs into global traces; iteratively training a similarity model to project the local traces into a vector space such that the pairs that are linked to common global traces exhibit a greater similarity with one another than the pairs that are linked to different global traces; and based on the similarity model as trained, linking further local traces to the global traces.

Abstract: An example embodiment may involve identifying local traces of related events within a plurality of event data repositories, wherein each of the event data repositories is respectively associated with a software application; using a clustering model, assigning the local traces into clusters; determining positive rules that define when pairs of the local traces are linked to a common global trace, and negative rules that define when the pairs are linked to different global traces; linking the pairs into global traces; iteratively training a similarity model to project the local traces into a vector space such that the pairs that are linked to common global traces exhibit a greater similarity with one another than the pairs that are linked to different global traces; and based on the similarity model as trained, linking further local traces to the global traces.

Abstract: An example embodiment may involve identifying local traces of related events within a plurality of event data repositories, wherein each of the event data repositories is respectively associated with a software application; using a clustering model, assigning the local traces into clusters; determining positive rules that define when pairs of the local traces are linked to a common global trace, and negative rules that define when the pairs are linked to different global traces; linking the pairs into global traces; iteratively training a similarity model to project the local traces into a vector space such that the pairs that are linked to common global traces exhibit a greater similarity with one another than the pairs that are linked to different global traces; and based on the similarity model as trained, linking further local traces to the global traces.

Abstract: An embodiment involves receiving a request specifying a particular process, wherein an event table associates event identifiers of events, process identifiers of processes that generated to the events, timestamps of times when the events occurred, states of the processes at the times, and references to related processes; generating nodes of a graph, wherein the particular process and each of its related processes are represented by entity nodes annotated with respective process identifiers, and the events are represented by event nodes annotated with respective event identifiers; generating edges between the entity nodes and the event nodes for which the events of the event nodes either were: generated by the processes represented by the entity nodes, or refer to the processes represented by the entity nodes; and generating edges between pairs of the event nodes that: generated by a common process, and the events of which occurred sequentially according to their timestamps.

Abstract: A speaker system is provided having a line array of drivers wired in parallel and treated with passive or active component systems that serve to electrically taper its effective radiating length with frequency so that it is long/tall at low frequencies and short at higher frequencies, with the effective length of the array determined so as to maintain a listener in the nearfield at typical home and studio listening distances while minimizing the destructive effects of path-length dependent high frequency comb filtering. In alternate embodiments, an array of drivers is provided and wired in series or series-parallel with passive components between the output of one driver and the input of the next. Schemes of active drive and combination schemes of active and passive drive are also contemplated.

Abstract: A speaker system is provided having a line array of drivers wired in parallel and treated with passive or active component systems that serve to electrically taper its effective radiating length with frequency so that it is long/tall at low frequencies and short at higher frequencies, with the effective length of the array determined so as to maintain a listener in the nearfield at typical home and studio listening distances while minimizing the destructive effects of path-length dependent high frequency comb filtering. In alternate embodiments, an array of drivers is provided and wired in series or series-parallel with passive components between the output of one driver and the input of the next. Schemes of active drive and combination schemes of active and passive drive are also contemplated.

Abstract: An integrated circuit having a temperature sensitive circuit (TSC) to generate a signal indicative of the substrate temperature near the TSC. The integrated circuit has circuitry configured to receive a TSC signal from at least one TSC and to convert the TSC signal to a signal indicative of the integrated circuit's temperature. The thermal control circuit compares the integrated circuit temperature to a threshold and produces a corrective action signal when the temperature exceeds the threshold. The corrective action signal is provided to corrective action circuitry preferably configured to modify the operation of the IC to reduce the IC temperature in proximity to the corresponding TSC.

Abstract: A microprocessor includes a functional block having dynamic power savings circuitry, a functional block control circuit, and a thermal control unit. The functional block control circuits are capable of altering performance characteristics of their associated functional blocks automatically upon detecting an over temperature condition. The thermal control unit receives an over-temperature signal indicating a processor temperature exceeding a threshold and invokes the one or more of the functional block control units in response to the signal. The functional block control units respond to signals from the thermal control unit by reducing processor activity, slowing processor performance, or both. The reduced activity that results causes the dynamic power saving circuitry to engage. The functional block control units can throttle performance by numerous means including reducing the exploitable parallelism within the processor, suspending out-of-order execution, reducing effective resource size, and the like.

Abstract: The present invention provides a temperature sensitive ring oscillator (TSRO) in an integrated circuit. A temperature measuring device, such as a thermal resistor, is proximate the TSRO, which shares a substantially similar temperature. A memory is employable for storing data that is a function of the output of the TSRO and the temperature measuring device.

Abstract: An improved method and system for integrated circuit device physical design and layout. The physical layout of the integrated circuit device is optimally stored in a database to provide improved analysis capabilities of the integrated circuit device's characteristics. The method and system evaluates local interactions between functional blocks and decoupling cells on a given floor plan of a chip using this optimized database in order to reduce memory and processor utilization. Local noise is projected by using dI/dt and capacitance estimates. Areas of highest noise concern are identified, and floor plan mitigation actions are taken by tuning the placement of neighboring decoupling cells and their properties. Upon several iterative cycles, a near optimal solution for a given floor plan of the total chip is achieved.

Abstract: Disclosed is an apparatus incorporating hardware based logic and a predetermined default list of software affecting responses to be taken in connection with temperatures sensed by thermal sensors checking the temperature of portions of computer logic. At the time application software is loaded, the software can modify the default response list. The list of responses to be taken and the over temperature conditions at which they are to be activated are stored in hardware directly accessible by hardware based thermal sensor monitoring logic for direct control of the hardware. The control can alter conditions such as clock frequency, stopping use of application software, interrupting OS functionality, removing power from components and so forth.

Abstract: A method and apparatus for reducing power consumption of a clocked circuit containing a plurality of latches is provided. A first latch, within the plurality of latches, is located which has more than a predetermined slack. The possibility of substituting an available second latch, that requires less power to operate, is then determined, subject to the constraint that the slack after substitution should still be positive, although it may be less than the predetermined number mentioned above. Where such a possibility is determined to exist, the first latch is then replaced with the available second latch.

Abstract: An on-chip thermal sensing circuit is disclosed. The thermal sensing circuit including a detection circuit located on an integrated circuit (IC) for detecting a local temperature of the IC. The output of the thermal sensor has a frequency that is directly related to the local temperature. The detection circuit has an associated time constant that is used to produce the frequency.

Abstract: A device for fault testing in a microprocessor chip provides a LBIST circuit which has a first reference signature. A loading unit is further provided for receiving and outputting a set of masking data. A file unit connected to the loading unit is yet further provided for receiving the masking data. A masking unit connected to the file unit is yet further provided for generating a second reference signature based on the masking data from the file unit and a scanning data from a scan string in the chip. And, a signature logic connected to the output of the masking unit is yet further provided for compressing the second reference signature and inputting the compressed second reference signature to the LBIST circuit, wherein the compressed second reference signature replaces the first reference signature.

Abstract: The present invention provides an integrated circuit VLSI temperature system for the calibration of threshold temperatures. A temperature sensitive ring oscillator (TSRO) generates a TSRO calibration parameter. A memory is employable to store the TSRO calibration parameter. A module is employable to determine a threshold TSRO oscillation frequency from the TSRO calibration parameter. A memory is employable for storing at least one threshold TSRO oscillation frequency.

Abstract: An improved method and system for integrated circuit device physical design and layout. The physical layout of the integrated circuit device is optimally stored in a database to provide improved analysis capabilities of the integrated circuit device's characteristics. The method and system evaluates local interactions between functional blocks and decoupling cells on a given floor plan of a chip using this optimized database in order to reduce memory and processor utilization. Local noise is projected by using dI/dt and capacitance estimates. Areas of highest noise concern are identified, and floor plan mitigation actions are taken by tuning the placement of neighboring decoupling cells and their properties. Upon several iterative cycles, a near optimal solution for a given floor plan of the total chip is achieved.

Abstract: A microprocessor includes a functional block having dynamic power savings circuitry, a functional block control circuit, and a thermal control unit. The functional block control circuits are capable of altering performance characteristics of their associated functional blocks automatically upon detecting an over temperature condition. The thermal control unit receives an over-temperature signal indicating a processor temperature exceeding a threshold and invokes the one or more of the functional block control units in response to the signal. The functional block control units respond to signals from the thermal control unit by reducing processor activity, slowing processor performance, or both. The reduced activity that results causes the dynamic power saving circuitry to engage. The functional block control units can throttle performance by numerous means including reducing the exploitable parallelism within the processor, suspending out-of-order execution, reducing effective resource size, and the like.

Abstract: Disclosed is an apparatus incorporating hardware based logic and a predetermined default list of software affecting responses to be taken in connection with temperatures sensed by thermal sensors checking the temperature of portions of computer logic. At the time application software is loaded, the software can modify the default response list. The list of responses to be taken and the over temperature conditions at which they are to be activated are stored in hardware directly accessible by hardware based thermal sensor monitoring logic for direct control of the hardware. The control can alter conditions such as clock frequency, stopping use of application software, interrupting OS functionality, removing power from components and so forth.

Abstract: An integrated circuit having a temperature sensitive circuit (TSC) to generate a signal indicative of the substrate temperature near the TSC. The integrated circuit has circuitry configured to receive a TSC signal from at least one TSC and to convert the TSC signal to a signal indicative of the integrated circuit's temperature. The thermal control circuit compares the integrated circuit temperature to a threshold and produces a corrective action signal when the temperature exceeds the threshold. The corrective action signal is provided to corrective action circuitry preferably configured to modify the operation of the IC to reduce the IC temperature in proximity to the corresponding TSC.

Abstract: The present invention provides an integrated circuit VLSI temperature system for the calibration of threshold temperatures. A temperature sensitive ring oscillator (TSRO) generates a TSRO calibration parameter. A memory is employable to store the TSRO calibration parameter. A module is employable to determine a threshold TSRO oscillation frequency from the TSRO calibration parameter. A memory is employable for storing at least one threshold TSRO oscillation frequency.