Patents by Inventor Joachim Hirschler
Joachim Hirschler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230395539Abstract: A method of manufacturing a semiconductor device includes forming a wiring metal layer structure; forming a dielectric layer structure arranged directly on the wiring metal layer structure; and forming a bonding pad metal layer structure arranged, at least partially, directly on the dielectric layer structure, wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure, wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.Type: ApplicationFiled: August 18, 2023Publication date: December 7, 2023Inventors: Evelyn Napetschnig, Jens Brandenburg, Christoffer Erbert, Joachim Hirschler, Oliver Humbel, Thomas Rupp, Carsten Schaeffer, Julia Zischang
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Patent number: 11764176Abstract: A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.Type: GrantFiled: August 12, 2021Date of Patent: September 19, 2023Assignee: Infineon Technologies AGInventors: Evelyn Napetschnig, Jens Brandenburg, Christoffer Erbert, Joachim Hirschler, Oliver Humbel, Thomas Rupp, Carsten Schaeffer, Julia Zischang
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Publication number: 20230082571Abstract: A power semiconductor device includes a semiconductor body and a first terminal at the semiconductor body. The first terminal has a first side for adjoining an encapsulation and a second side for adjoining the semiconductor body. The first terminal includes, at the first side, a top layer; and, at the second side, a base layer coupled with the top layer, wherein a sidewall of the top layer and/or a sidewall of the base layer is arranged in an angle smaller than 85° with respect to a plane.Type: ApplicationFiled: September 15, 2022Publication date: March 16, 2023Inventors: Jochen HILSENBECK, Thomas SOELLRADL, Roman ROTH, Annette SAENGER, Ulrike FASTNER, Johanna SCHLAMINGER, Joachim HIRSCHLER, Andreas BEHRENDT
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Publication number: 20220059477Abstract: A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.Type: ApplicationFiled: August 12, 2021Publication date: February 24, 2022Inventors: Evelyn Napetschnig, Jens Brandenburg, Christoffer Erbert, Joachim Hirschler, Oliver Humbel, Thomas Rupp, Carsten Schaeffer, Julia Zischang
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Patent number: 11195713Abstract: In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100° C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.Type: GrantFiled: May 30, 2019Date of Patent: December 7, 2021Assignee: Infineon Technologies AGInventors: Joachim Hirschler, Georg Ehrentraut, Christoffer Erbert, Klaus Goeschl, Markus Heinrici, Michael Hutzler, Wolfgang Koell, Stefan Krivec, Ingmar Neumann, Mathias Plappert, Michael Roesner, Olaf Storbeck
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Publication number: 20190385842Abstract: In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100° C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.Type: ApplicationFiled: May 30, 2019Publication date: December 19, 2019Inventors: Joachim Hirschler, Georg Ehrentraut, Christoffer Erbert, Klaus Goeschl, Markus Heinrici, Michael Hutzler, Wolfgang Koell, Stefan Krivec, Ingmar Neumann, Mathias Plappert, Michael Roesner, Olaf Storbeck
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Patent number: 10453806Abstract: A method for forming a semiconductor device and semiconductor device is disclosed. In one example, the method includes forming a silicone layer on a semiconductor die. The method further includes plasma treating a silicone surface of the silicone layer. A surfactant is deposited on the plasma-treated silicone surface of the silicone layer to obtain a silicone surface at least partly covered by surfactant. A mold is formed on the silicone surface at least partly covered by surfactant. The surfactant includes surfactant molecules comprising an inorganic skeleton terminated by organic compounds.Type: GrantFiled: November 14, 2017Date of Patent: October 22, 2019Assignee: Infineon Teohnologies Austria AGInventors: Joachim Hirschler, Christoffer Erbert, Markus Heinrici, Mathias Plappert, Caterina Travan
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Patent number: 10195704Abstract: Lift pins and devices having lift pins are provided. According to an aspect, a lift pin may have a tapered distal portion. According to another aspect, a lift pin may have two portions threadedly engaged with each other. According to yet another aspect, a lift pin may be mounted to a lifting plate with slackness.Type: GrantFiled: March 15, 2013Date of Patent: February 5, 2019Assignee: Infineon Technologies AGInventors: Christian Himmelsbach, Joachim Hirschler, Helmut Brunner
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Patent number: 10170746Abstract: A battery electrode in accordance with various embodiments may include: a substrate including a surface configured to face an ion-carrying electrolyte; and a first diffusivity changing region at a first portion of the surface, wherein the first diffusivity changing region is configured to change diffusion of ions carried by the electrolyte into the substrate, and wherein a second portion of the surface is free from the first diffusivity changing region.Type: GrantFiled: October 17, 2012Date of Patent: January 1, 2019Assignee: Infineon Technologies AGInventors: Joachim Hirschler, Magdalena Forster, Michael Sorger, Katharina Schmut, Bernhard Goller, Philemon Schweizer, Michael Sternad, Thomas Walter
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Publication number: 20180145038Abstract: A method for forming a semiconductor device and semiconductor device is disclosed. In one example, the method includes forming a silicone layer on a semiconductor die. The method further includes plasma treating a silicone surface of the silicone layer. A surfactant is deposited on the plasma-treated silicone surface of the silicone layer to obtain a silicone surface at least partly covered by surfactant. A mold is formed on the silicone surface at least partly covered by surfactant. The surfactant includes surfactant molecules comprising an inorganic skeleton terminated by organic compounds.Type: ApplicationFiled: November 14, 2017Publication date: May 24, 2018Applicant: Infineon Technologies Austria AGInventors: Joachim Hirschler, Christoffer Erbert, Markus Heinrici, Mathias Plappert, Caterina Travan
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Patent number: 9905147Abstract: A display device is provided. The display device comprises a display comprising a plurality of pixels arranged in a display plane. The display device is configured to determine a virtual plane at which a long-sighted user of the display device who is looking at the display sees sharp. Further, the display device is configured to determine a first contiguous group of pixels of the display which are located within a first optical path from a first virtual pixel of the virtual plane to an eye of the long-sighted user, and to determine a second contiguous group of pixels of the display which are located within a second optical path from a second virtual pixel of the virtual plane to the eye of the long-sighted user.Type: GrantFiled: August 21, 2015Date of Patent: February 27, 2018Assignee: Infineon Technologies AGInventors: Joachim Hirschler, Johann Schmid
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Patent number: 9673096Abstract: According to various embodiments, a method for processing a semiconductor substrate may include: covering a plurality of die regions of the semiconductor substrate with a metal; forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal; and, subsequently, annealing the metal covering at least one die of the plurality of dies.Type: GrantFiled: November 14, 2014Date of Patent: June 6, 2017Assignees: INFINEON TECHNOLOGIES AG, Technische Universitaet GrazInventors: Joachim Hirschler, Michael Roesner, Markus Juch Heinrici, Gudrun Stranzl, Martin Mischitz, Martin Zgaga
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Patent number: 9614045Abstract: In various embodiments, a method of processing a semiconductor device may include providing a semiconductor device comprising a contact pad and a polymer layer; and subjecting at least a part of the contact pad and the polymer layer to a plasma comprising ammonia.Type: GrantFiled: September 17, 2014Date of Patent: April 4, 2017Assignee: INFINEON TECHNOLOGIES AGInventors: Srinivasa Reddy Yeduru, Joachim Hirschler, Harald Wiedenhofer, Franz Kleinbichler
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Patent number: 9511560Abstract: A method for processing a sacrificial material of an intermediate microfabricated product includes forming a hydrogen-containing carbon layer on a surface of a base structure and releasing hydrogen from the hydrogen-containing carbon layer to obtain a hydrogen-released (i.e., densified) carbon layer with low shrink. The method further includes forming a structural layer on at least a portion of a surface of the hydrogen-released carbon layer, and oxidizing the hydrogen-released (densified) carbon layer to release the structural layer. In this manner, a cavity is formed between the base structure and the structural layer. The ashing of the hydrogen-released carbon layer leaves substantially no residues within the cavity of the intermediate or final microfabricated product. Further embodiments provide a method for manufacturing a microfabricated product, to an intermediate microfabricated product, and to a microfabrication equipment.Type: GrantFiled: April 13, 2012Date of Patent: December 6, 2016Assignee: Infineon Technologies AGInventors: Guenter Denifl, Daniel Maurer, Thomas Grille, Joachim Hirschler, Markus Kahn
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Patent number: 9455192Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes attaching a substrate to a carrier using an adhesive component and forming a through trench through the substrate to expose the adhesive component. At least a portion of the adhesive component is etched and a metal layer is formed over sidewalls of the through trench.Type: GrantFiled: March 26, 2014Date of Patent: September 27, 2016Assignee: Infineon Technologies AGInventors: Michael Roesner, Manfred Engelhardt, Johann Schmid, Gudrun Stranzl, Joachim Hirschler
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Patent number: 9449928Abstract: A layer arrangement in accordance with various embodiments may include: a wafer; a passivation disposed over the wafer; a protection layer disposed over at least a surface of the passivation facing away from the wafer; and a mask layer disposed over at least a surface of the protection layer facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation, and wherein the mask layer includes a material that is selectively etchable to the material of the protection layer.Type: GrantFiled: April 15, 2014Date of Patent: September 20, 2016Assignee: Infineon Technologies AGInventors: Joachim Hirschler, Gudrun Stranzl
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Publication number: 20160204017Abstract: Various embodiments provide a method of picking up a chip from a carrier system, wherein the method comprises providing a carrier system comprising a plurality of chips comprising edge portions and being attached to a one surface of the carrier system by an adhesive layer; embrittling the adhesive layer selectively at the edge portions of the plurality of chips; and picking up at least one chip of the plurality of chips.Type: ApplicationFiled: January 13, 2016Publication date: July 14, 2016Inventors: Michael Roesner, Chu Hua Goh, Markus Heinrici, Joachim Hirschler, Irina Mueller
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Publication number: 20160079087Abstract: In various embodiments, a method of processing a semiconductor device may include providing a semiconductor device comprising a contact pad and a polymer layer; and subjecting at least a part of the contact pad and the polymer layer to a plasma comprising ammonia.Type: ApplicationFiled: September 17, 2014Publication date: March 17, 2016Inventors: SRINIVASA REDDY YEDURU, JOACHIM HIRSCHLER, HARALD WIEDENHOFER, FRANZ KLEINBICHLER
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Publication number: 20150356907Abstract: A display device is provided. The display device comprises a display comprising a plurality of pixels arranged in a display plane. The display device is configured to determine a virtual plane at which a long-sighted user of the display device who is looking at the display sees sharp. Further, the display device is configured to determine a first contiguous group of pixels of the display which are located within a first optical path from a first virtual pixel of the virtual plane to an eye of the long-sighted user, and to determine a second contiguous group of pixels of the display which are located within a second optical path from a second virtual pixel of the virtual plane to the eye of the long-sighted user.Type: ApplicationFiled: August 21, 2015Publication date: December 10, 2015Inventors: Joachim Hirschler, Johann Schmid
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Publication number: 20150279740Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes attaching a substrate to a carrier using an adhesive component and forming a through trench through the substrate to expose the adhesive component. At least a portion of the adhesive component is etched and a metal layer is formed over sidewalls of the through trench.Type: ApplicationFiled: March 26, 2014Publication date: October 1, 2015Applicant: INFINEON TECHNOLOGIES AGInventors: Michael Roesner, Manfred Engelhardt, Johann Schmid, Gudrun Stranzl, Joachim Hirschler