Abstract: A method for preparing a monocrystalline silicon substrate surface for a subsequent texturing step, the method comprising: removing contaminants from the surface by contacting the surface with a cleaning solution; etching the pre-cleaned surface with an aqueous solution comprising from 12 to 19% by weight, of KOH and/or NaOH; rinsing the etched surface with an aqueous medium at pH from 7 to 10; and contacting the rinsed etched surface with ozonated deionized water at pH from 2 to 4.5, thereby converting the rinsed etched surface into a prepared surface. A method for texturing the prepared surface is also provided.

Abstract: A method for preparing a monocrystalline silicon substrate surface for a subsequent texturing step, the method comprising: removing contaminants from the surface by contacting the surface with a cleaning solution; etching the pre-cleaned surface with an aqueous solution comprising from 12 to 19% by weight, of KOH and/or NaOH; rinsing the etched surface with an aqueous medium at pH from 7 to 10; and contacting the rinsed etched surface with ozonated deionized water at pH from 2 to 4.5, thereby converting the rinsed etched surface into a prepared surface. A method for texturing the prepared surface is also provided.

Abstract: The present invention is related to a method for forming a metal silicide layer on a textured silicon substrate surface. The method includes providing a metal layer on a textured silicon substrate and performing a pulsed laser annealing step providing at least one UV laser pulse with a laser fluence in the range between 0.1 J/cm2 and 1.5 J/cm2 and with a laser pulse duration in the range between 1 ns and 10 ms. Then, the method includes converting at least part of the metal layer into a metal silicide layer. In addition, the present invention is related to the use of such a method in a process for fabricating a photovoltaic cell, wherein the dielectric layer is a surface passivation layer, or wherein the dielectric layer is an antireflection coating.

Abstract: A method for single side texturing of a crystalline semiconductor substrate (10) comprises: providing a substrate (10), for example a semiconductor substrate, comprising a first surface (12) and a second surface (14) opposite to one another with respect to the substrate (10); providing a masking layer (21) with a random pattern on the first surface (12) of the substrate (10); and etching the substrate (10) in a polishing solution, thereby texturing the first surface (12) of the substrate (10) and polishing the second surface (14) in a single wet etching step.

Abstract: The present invention is related to a method for forming a metal silicide layer on a textured silicon substrate surface. The method includes providing a metal layer on a textured silicon substrate and performing a pulsed laser annealing step providing at least one UV laser pulse with a laser fluence in the range between 0.1 J/cm2 and 1.5 J/cm2 and with a laser pulse duration in the range between 1 ns and 10 ms. Then, the method includes converting at least part of the metal layer into a metal silicide layer. In addition, the present invention is related to the use of such a method in a process for fabricating a photovoltaic cell, wherein the dielectric layer is a surface passivation layer, or wherein the dielectric layer is an antireflection coating.

Abstract: A method for single side texturing of a crystalline semiconductor substrate (10) comprises: providing a substrate (10), for example a semiconductor substrate, comprising a first surface (12) and a second surface (14) opposite to one another with respect to the substrate (10); providing a masking layer (21) with a random pattern on the first surface (12) of the substrate (10); and etching the substrate (10) in a polishing solution, thereby texturing the first surface (12) of the substrate (10) and polishing the second surface (14) in a single wet etching step.

Abstract: The present invention is related to a method for providing solder material on a predetermined area on a substrate. In various embodiments, the solder material is deposited on a wetting layer which lies within an area on a substrate having a confinement layer. Further a packaging method and package are disclosed.

Abstract: In the preferred embodiments, a method to reduce gate leakage and dispersion of group III-nitride field effect devices covered with a thin in-situ SiN layer is provided. This can be obtained by introducing a second passivation layer on top of the in-situ SiN-layer, in combination with cleaning of the in-situ SiN before gate deposition and before deposition of the second passivation layer.

Abstract: In the preferred embodiments, a method to reduce gate leakage and dispersion of group III-nitride field effect devices covered with a thin in-situ SiN layer is provided. This can be obtained by introducing a second passivation layer on top of the in-situ SiN-layer, in combination with cleaning of the in-situ SiN before gate deposition and before deposition of the second passivation layer.

Abstract: The present invention is related to a method for providing solder material on a predetermined area on a substrate. In various embodiments, the solder material is deposited on a wetting layer which lies within an area on a substrate having a confinement layer. Further a packaging method and package are disclosed.