Abstract: A semiconductor device and a method for fabricating the semiconductor device. The device includes: a doped semiconductor having a source region, a drain region, a channel between the source and drain regions, and an extension region between the channel and each of the source and drain regions; a gate formed on the channel; and a screening coating on each of the extension regions. The screening coating includes: (i) an insulating layer that has a dielectric constant that is no greater than about half that of the extension regions and is formed directly on the extension regions, and (ii) a screening layer on the insulating layer, where the screening layer screens the dopant ionization potential in the extension regions to inhibit dopant deactivation.

Abstract: An Impact Ionization Field-Effect Transistor (I-MOS) device in which device degradation caused by hot carrier injection into a gate oxide is prevented. The device includes source, drain, and gate contacts, and a channel between the source and the drain. The channel has a dimension normal to the direction of a charge carrier transport in the channel such that the energy separation of the first two sub-bands equals or exceeds the effective energy band gap of the channel material.

Abstract: A semiconductor device and a method for fabricating the semiconductor device. The device includes: a doped semiconductor having a source region, a drain region, a channel between the source and drain regions, and an extension region between the channel and each of the source and drain regions; a gate formed on the channel; and a screening coating on each of the extension regions. The screening coating includes: (i) an insulating layer that has a dielectric constant that is no greater than about half that of the extension regions and is formed directly on the extension regions, and (ii) a screening layer on the insulating layer, where the screening layer screens the dopant ionization potential in the extension regions to inhibit dopant deactivation.

Abstract: An indirectly induced tunnel emitter for a tunneling field effect transistor (TFET) structure includes an outer sheath that at least partially surrounds an elongated core element, the elongated core element formed from a first semiconductor material; an insulator layer disposed between the outer sheath and the core element; the outer sheath disposed at a location corresponding to a source region of the TFET structure; and a source contact that shorts the outer sheath to the core element; wherein the outer sheath is configured to introduce a carrier concentration in the source region of the core element sufficient for tunneling into a channel region of the TFET structure during an on state.

Abstract: An electronic device and method of manufacturing the device. The device includes a semiconducting region, which can be a nanowire, a first contact electrically coupled to the semiconducting region, and at least one second contact capacitively coupled to the semiconducting region. At least a portion of the semiconducting region between the first contact and the second contact is covered with a dipole layer. The dipole layer can act as a local gate on the semiconducting region to enhance the electric properties of the device.

Abstract: A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes a superlattice structure wherein a mini-band is formed. The energy filter is operative to control an injection of carriers from the first source/drain into the channel. The energy filter, in combination with the first source/drain, is configured to produce an effective zero-Kelvin first source/drain.

Abstract: A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes an impurity band operative to control an injection of carriers from the first source/drain into the channel.

Abstract: An indirectly induced tunnel emitter for a tunneling field effect transistor (TFET) structure includes an outer sheath that at least partially surrounds an elongated core element, the elongated core element formed from a first semiconductor material; an insulator layer disposed between the outer sheath and the core element; the outer sheath disposed at a location corresponding to a source region of the TFET structure; and a source contact that shorts the outer sheath to the core element; wherein the outer sheath is configured to introduce a carrier concentration in the source region of the core element sufficient for tunneling into a channel region of the TFET structure during an on state.

Abstract: An Impact Ionization Field-Effect Transistor (I-MOS) device in which device degradation caused by hot carrier injection into a gate oxide is prevented. The device includes source, drain, and gate contacts, and a channel between the source and the drain. The channel has a dimension normal to the direction of a charge carrier transport in the channel such that the energy separation of the first two sub-bands equals or exceeds the effective energy band gap of the channel material.

Abstract: A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes an impurity band operative to control an injection of carriers from the first source/drain into the channel.

Abstract: An electronic device and method of manufacturing the device. The device includes a semiconducting region, which can be a nanowire, a first contact electrically coupled to the semiconducting region, and at least one second contact capacitively coupled to the semiconducting region. At least a portion of the semiconducting region between the first contact and the second contact is covered with a dipole layer. The dipole layer can act as a local gate on the semiconducting region to enhance the electric properties of the device.

Abstract: A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes an impurity band operative to control an injection of carriers from the first source/drain into the channel.

Abstract: A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes a superlattice structure wherein a mini-band is formed. The energy filter is operative to control an injection of carriers from the first source/drain into the channel. The energy filter, in combination with the first source/drain, is configured to produce an effective zero-Kelvin first source/drain.

Abstract: A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes an impurity band operative to control an injection of carriers from the first source/drain into the channel.

Abstract: A method of fabricating a tunneling nanotube field effect transistor includes forming in a nanotube an n-doped region and a p-doped region which are separated by an undoped channel region of the transistor. Electrical contacts are provided for the doped regions and a gate electrode that is formed upon a gate dielectric layer deposited on at least a portion of the channel region of the transistor.

Abstract: A method of fabricating a tunneling nanotube field effect transistor includes forming in a nanotube an n-doped region and a p-doped region which are separated by an undoped channel region of the transistor. Electrical contacts are provided for the doped regions and a gate electrode that is formed upon a gate dielectric layer deposited on at least a portion of the channel region of the transistor.