Abstract: The invention refers to analyzing a digitally modulated test signal received from a device under test -DUT-, comprising providing a first sampled signal by assigning a first sequence of digital values as result of a level comparison of the test signal with a first threshold at first successive timing points, generating a first masking signal indicating matches between a second sequence of digital values expected from the DUT and one or a plurality of first data patterns, and analyzing the first sampled signal in conjunction with the masking signal.

Abstract: An integrated circuit (10), preferably a field programmable gate array—FPGA or an application specific integrated circuit—ASIC—, comprises a level comparator (30) for comparing a level of a comparator input signal and correspondingly providing a comparator output signal (COS). A sampling unit (40) is coupled to the level comparator (30) for sampling (SAM) the comparator output signal (COS). A bit error test unit (60) receives the sampled comparator output signal (SAM) and determine therefrom an indication of a bit error in a sequence of the sampled comparator output signal (SAM).

Abstract: For testing a digital data signal, a value derived from the digital data signal at a sampling point is compared against a corresponding value of an arbitrary test signal. The comparison is interpreted as an error in case the derived value does not substantially match with the corresponding value of the arbitrary test signal.

Abstract: Determining a jitter property of a signal with a repetitive bit sequence of a plurality of bits includes setting a sample point at a first sampling position relative to a first transition within the bit pattern, assigning a set of digital values to comparison results of the digital signal with a threshold at the set sample point for a plurality of repetitions of the bit sequence, determining a distribution value on the base of the sum of the assigned digital values, shifting the sample point by a time increment, iteratively repeating determining the distribution value until the sample point has reached a second sampling position, determining from the distribution values a distribution function over the sample points, and determining the jitter property by using the distribution function.

Abstract: Testing a device under test—DUT—includes providing a test signal from the DUT to a test probe, taking from the test signal being present at the test probe analog samples at a first sampling rate, taking from the test signal being present at the test probe digital samples at a second sampling rate, providing a control signal indicative of sampling times of the analog samples, and performing an analysis of the digital samples in conjunction with the control signal.

Abstract: A noise signal generator includes a random word generator for generating a sequence of random words, each word representing an input value, a mapping unit for receiving the sequence of random words, mapping each input value to an output value of according to a probability distribution function, and providing a corresponding sequence of output values, and a digital-to-analog converter for generating a noise signal based on the output values.

Abstract: The invention refers to analyzing a digitally modulated test signal received from a device under test -DUT-, comprising providing a first sampled signal by assigning a first sequence of digital values as result of a level comparison of the test signal with a first threshold at first successive timing points, generating a first masking signal indicating matches between a second sequence of digital values expected from the DUT and one or a plurality of first data patterns, and analyzing the first sampled signal in conjunction with the masking signal.

Abstract: Testing a device under test—DUT—includes providing a test signal from the DUT to a test probe, taking from the test signal being present at the test probe analog samples at a first sampling rate, taking from the test signal being present at the test probe digital samples at a second sampling rate, providing a control signal indicative of sampling times of the analog samples, and performing an analysis of the digital samples in conjunction with the control signal.

Abstract: Time characteristics of a data signal including a sequence of a plurality of bits are determined by a method including providing a first trigger signal in response to a clock signal related to the data signal, providing first sample values from the data signal, in response to the first trigger signal, and providing a signal analysis based on the first sample values in conjunction with bit values of the data signal in a certain time range with respect to the first trigger signal.

Abstract: The present invention relates to a method and a corresponding system for generating a binary pulse stream (37) based on a stable clock (76), said method being characterized by the steps of: reading a sequence of pairs of values representing LOW and HIGH state duration, respectively, of consecutive pulses of said binary pulse stream (37), said pairs of values being related to said stable clock (76), providing for each value an integral multiple part and a fractional part of the cycle time of said stable clock (76), using said integral multiple part for controlling an edge forming unit (40), said edge forming unit (40) contributes said integral multiple part of the duration of the respective state of the respective pulse to said binary pulse stream (37) to be generated, and using said fractional part for controlling a delay modulation unit (42), said delay modulation unit (42) prolongs, according to said fractional part, the duration of the respective state of the respective pulse to said binary pulse stream (3

Abstract: For testing a digital data signal, a value derived from the digital data signal at a sampling point is compared against a corresponding value of an arbitrary test signal. The comparison is interpreted as an error in case the derived value does not substantially match with the corresponding value of the arbitrary test signal.

Abstract: An integrated circuit (10), preferably a field programmable gate array—FPGA or an application specific integrated circuit—ASIC—, comprises a level comparator (30) for comparing a level of a comparator input signal and correspondingly providing a comparator output signal (COS). A sampling unit (40) is coupled to the level comparator (30) for sampling (SAM) the comparator output signal (COS). A bit error test unit (60) receives the sampled comparator output signal (SAM) and determine therefrom an indication of a bit error in a sequence of the sampled comparator output signal (SAM).

Abstract: A coupling unit that couples at least two pins of an ATE (Automated Test Equipment) to a pin of a device under test includes an ATE interface for receiving a plurality of first stimulus signals from selected ATE-pins and/or for sending a plurality of first response signals to the selected ATE-pins, a DUT interface for sending a second stimulus signal to the DUT-pin and/or for receiving a second response signal from the DUT-pin, and a multiplexer circuit for serializing data of the plurality of first stimulus signals into the second stimulus signal and/or a de-multiplexer circuit adapted for parallelizing data of the second response signal into the plurality of first response signals.

Abstract: Determining a jitter property of a signal with a repetitive bit sequence of a plurality of bits includes setting a sample point at a first sampling position relative to a first transition within the bit pattern, assigning a set of digital values to comparison results of the digital signal with a threshold at the set sample point for a plurality of repetitions of the bit sequence, determining a distribution value on the base of the sum of the assigned digital values, shifting the sample point by a time increment, iteratively repeating determining the distribution value until the sample point has reached a second sampling position, determining from the distribution values a distribution function over the sample points, and determining the jitter property by using the distribution function.

Abstract: The invention relates to noise signal generator, comprising a random word generator for generating a sequence of random words, each word representing an input value, a mapping unit for receiving the sequence of random words, mapping each input value to an output value of according to a probability distribution function, and providing a corresponding sequence of output values, and a digital-to-analog converter for generating a noise signal based on the output values.

Abstract: The invention relates to a signal generator for generating a sequence of digital values according to a reference clock signal, comprising at least one input terminal for receiving a an increment signal and an offset signal, a start value circuit adapted for determining a counter start value on the base of the offset signal and the increment signal, a counter being adapted to be set to the start value, and to change the counter position at each cycle of the reference clock signal to a new value according to the increment signal until a defined value is achieved, and an output terminal for outputting the counter values.

Abstract: A signal shaping circuit for shaping a test signal to be provided to a device under test includes a first signal path with a first transmission behavior and adapted to receive an input signal, and at least one second signal path with a second transmission behavior and adapted to receive an input signal, wherein the outputs of the signal paths are connected to a signal combiner adapted to combine the output signals of the signal paths to the test signal as an output signal of the signal shaping circuit.

Abstract: A signal-analyzing unit has a sampling path and a reference path both receiving a digital test signal. The sampling path has a first comparator for comparing the test signal against a first threshold value and providing a first comparison signal, and a first sampling device receiving as input the first comparison signal and a first timing signal. The reference path has a second comparator for comparing the test signal against a second threshold value and providing a second comparison signal, and a second sampling device for receiving as input the second comparison signal and a second timing signal. An analysis unit receives and analyzes the output of the sampling and reference paths.

Abstract: A delay unit for providing an output signal delayed by a delay time with respect to a periodic signal received at its input, the delay unit comprises a first delay cell adapted to receive the periodic signal and to provide as output a first delayed signal corresponding to the input periodic signal but delayed by a variable first delay time. A selection unit receives the first delayed signal and a second signal derived from the periodic signal. A control unit controls the selection unit in order to select one of the first delayed signal and the second signal as the output signal of the delay unit, and further controls the first delay time of the first delay cell.

Abstract: A coupling unit that couples at least two pins of an ATE (Automated Test Equipment) to a pin of a device under test includes an ATE interface for receiving a plurality of first stimulus signals from selected ATE-pins and/or for sending a plurality of first response signals to the selected ATE-pins, a DUT interface for sending a second stimulus signal to the DUT-pin and/or for receiving a second response signal from the DUT-pin, and a multiplexer circuit for serializing data of the plurality of first stimulus signals into the second stimulus signal and/or a de-multiplexer circuit adapted for parallelizing data of the second response signal into the plurality of first response signals.