Patents by Inventor Joachim NEUBAUER

Joachim NEUBAUER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160370423
    Abstract: A testing device for electrically testing an electrical test specimen, in particular a wafer, the testing device having a test head in which at least one testing contact is mounted for electrically contacting a test specimen. At least one outlet opening for discharging a gas, in particular a protective gas, into a contact region, is provided in a wall of the test head.
    Type: Application
    Filed: April 15, 2014
    Publication date: December 22, 2016
    Applicant: FEINMETALL GMBH
    Inventors: Ulrich GAUSS, Joachim NEUBAUER, Stefan TREUZ, Jürgen HAAP
  • Patent number: 7403835
    Abstract: In a device and method for programming an industrial robot using a simulation program, control commands are issued by a handheld programming device and these commands are visualized on an image surface as movement and/or processing operations by the robot on the basis of data of the robot. An object to be processed is also displayed on the image surface and a three-dimensional image of the robot and the object is presented.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: July 22, 2008
    Assignee: Bayerische Motoren Werke Aktiengesellschaft
    Inventors: Harald Sandner, Hans-Joachim Neubauer
  • Publication number: 20060287772
    Abstract: In a device and method for programming an industrial robot using a simulation program, control commands are issued by a handheld programming device and these commands are visualized on an image surface as movement and/or processing operations by the robot on the basis of data of the robot. An object to be processed is also displayed on the image surface and a three-dimensional image of the robot and the object is presented.
    Type: Application
    Filed: May 19, 2006
    Publication date: December 21, 2006
    Applicant: Bayerische Motoren Werke Aktiengesellschaft
    Inventors: Harald Sandner, Hans-Joachim Neubauer
  • Patent number: 6917549
    Abstract: An integrated memory has a memory cell array having word lines and bit lines. The bit lines are organized in bit line pairs. The bit lines of the bit line pairs cross one another at a crossing location and run parallel to one another. A sense amplifier is connected to one of the bit line pairs at one end. Two precharge circuits are provided. One precharge circuit is arranged on a side of the crossing location and the other precharge circuit is arranged on a side of the crossing location. The precharge circuit facing the sense amplifier is arranged at a first distance from the crossing location and at a second distance from the sense amplifier. The RC constant of the bit lines, which is effective during the precharge operation, is reduced, so that the time period required for a precharge operation is reduced.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: July 12, 2005
    Assignee: Infineon Technologies AG
    Inventors: Manfred Pröll, Stephan Schröder, Heinz-Joachim Neubauer, Evangelos Stavrou
  • Publication number: 20040156253
    Abstract: An integrated memory has a memory cell array having word lines and bit lines. The bit lines are organized in bit line pairs. The bit lines of the bit line pairs cross one another at a crossing location and run parallel to one another. A sense amplifier is connected to one of the bit line pairs at one end. Two precharge circuits are provided. One precharge circuit is arranged on a side of the crossing location and the other precharge circuit is arranged on a side of the crossing location. The precharge circuit facing the sense amplifier is arranged at a first distance from the crossing location and at a second distance from the sense amplifier. The RC constant of the bit lines, which is effective during the precharge operation, is reduced, so that the time period required for a precharge operation is reduced.
    Type: Application
    Filed: January 20, 2004
    Publication date: August 12, 2004
    Inventors: Manfred Proll, Stephan Schroder, Heinz-Joachim Neubauer, Evangelos Stavrou
  • Publication number: 20040042289
    Abstract: An integrated memory circuit has a memory cell array and a test circuit. The memory cell array is formed with memory areas each having a number of cells. The test circuit generates error information during testing of an addressed memory area. The error information indicates if at least one of the cells of the addressed memory area is faulty. A storage element is provided which, given the occurrence of an error in the addressed memory area, stores information with the aid of which the faulty memory cell of the faulty area can be identified.
    Type: Application
    Filed: September 4, 2003
    Publication date: March 4, 2004
    Inventors: Manfred Proll, Claus Engelhardt, Heinz-Joachim Neubauer, Jorg Kliewer