Abstract: The cascode circuit comprises a plurality of switching transistors (11) to be protected from high voltage and a plurality of cascode transistors (13) connected to the switching transistors (11). A test node (B?) is arranged between each switching transistor (11) and its cascode transistor (13), and a test transistor (30.1-30.n) is allocated to each test node (B?), its gate being connected to the test node (B?). The sources of the test transistors (30.1-30.n) are connected to a first test point (31) and the drains of the test transistors (30.1-30.n) are connected to a second test point (32). A first voltage (U1) is applied to the first test point (31) and a second, slightly lower voltage (U2) is applied to the second test point (32). A current flow detected between the first (31) and the second (32) test point indicates that at least one of the cascode transistors (13) does not work correctly. Thus, the cascode circuit is testable.

Abstract: The invention relates to a one-time programmable memory device. In order to make such a memory device particular simple and reliable, it is proposed that the device comprises a MOS selection transistor T1 and a MOS memory transistor T2 connected in series between a voltage supply line BL and ground Gnd. The device further comprises programming means for applying predetermined voltages Vsel, Vctrl, Vprog to the gate of the selection transistor T1, to the gate of the memory transistor T2 and to the voltage supply line BL. The applied voltages Vsel, Vctrl, Vprog are selected such that they force the memory transistor T2 into a snap-back mode resulting in a current thermally damaging the drain junction of the memory transistor T2. The invention relates equally to a corresponding method for programming a one time programmable memory.

Abstract: The invention is a method and a computer program product for checking an integrated circuit for electrostatic discharge (ESD) robustness at the design level and comprises essentially the check of the layout of the integrated circuit against a set of rules defining one or more transistor geometric and/or electrical and/or material values and generating an output or report of this check. This method can check automatically a complete IC design layout at any design level. An exemplary design is an ESD protection layout, a design block or a complete IC design.

Abstract: The method relates to the preparation of a TEM lamella from a structured sample, in particular of a microelectronic device, which has a location to be examined, situated at an unknown position. Firstly, the structural element within which the region to be examined is situated is prelocalized. Afterwards, the TEM lamella is sectioned by means of an ion beam of an FIB apparatus with a thickness such that the entire structural element is contained in the TEM lamella. This method considerably increases the probability that the location to be examined will actually be situated in the TEM lamella, without the sample or lamella having to be transported too often.