Abstract: The invention relates to NPN and PNP bipolar transistors and to a method for the production thereof, said transistors being characterised by a particularly high collector-emitter and collector-base blocking voltage. The blocking voltage is increased by a particular doping profile. An NPN bipolar transistor comprises a p-doped substrate (1), a trenched n-doped layer (3) forming the collector, a p-doped layer (7) which is arranged above the trenched n-doped layer and is made of a base and an n-doped layer which is arranged within the p-doped layer and forms an emitter of the transistor. A spatial charge area (RLZ 1) is formed between the p-doped layer and the trenched n-doped layer and a second spatial charge area (RLZ 2) is formed between the trenched n-doped layer and the p-doped substrate, which expands in the vertical direction on the collector when the transistor is operated with an increasing potential.

Abstract: A method for fabricating integrable PMOSFET semiconductor structures in a P-doped substrate which are distinguished by a high dielectric strength is provided. In order to fabricate the PMOSFET semiconductor structure, a mask is applied to a semiconductor substrate for the definition of a window delimited by a peripheral edge. An N-doped well is thereupon produced in the P-doped semiconductor substrate by means of high-voltage ion implantation through the window delimited by the mask, the edge zone of said N-doped well reaching as far as the surface of the semiconductor substrate. The individual regions for the source, drain and bulk of the PMOSFET semiconductor structure are then produced in the P-doped inner zone enclosed by the well. The P-doped inner zone forms the drift zone of the PMOSFET structure. Since the drift zone has the weak basic doping of the substrate, the PMOSFET has a high dielectric strength.

Abstract: The invention relates to NPN and PNP bipolar transistors and to a method for the production thereof, said transistors being characterised by a particularly high collector-emitter and collector-base blocking voltage. The blocking voltage is increased by a particular doping profile. An NPN bipolar transistor comprises a p-doped substrate (1), a trenched n-doped layer (3) forming the collector, a p-doped layer (7) which is arranged above the trenched n-doped layer and is made of a base and an n-doped layer which is arranged within the p-doped layer and forms an emitter of the transistor. A spatial charge area (RLZ 1) is formed between the p-doped layer and the trenched n-doped layer and a second spatial charge area (RLZ 2) is formed between the trenched n-doped layer and the p-doped substrate, which expands in the vertical direction on the collector when the transistor is operated with an increasing potential.

Abstract: The invention relates to a method for producing integrable semiconductor components, especially transistors or logic gates, using a p-doped semiconductor substrate. First of all, a mask is applied to the semiconductor substrate in order to define a window that is delimited by a peripheral edge. An n-doped trough is then produced in the semiconductor substrate by means of ion implantation using an energy that is sufficient for ensuring that a p-doped inner area remains on the surface of the semiconductor substrate. The edge area of the n-doped trough extends as far as the surface of the semiconductor substrate. The other n-doped and/or p-doped areas that make up the structure of the transistor or logic gate are then inserted into the p-doped inner area of the semiconductor substrate. The inventive method is advantageous in that it no longer comprises expensive epitaxy and insulation processes. In an n-doped semiconductor substrate, all of the implanted ions are replaced by the complementary species; i.e.

Abstract: A method for fabricating integrable PMOSFET semiconductor structures in a P-doped substrate which are distinguished by a high dielectric strength is provided. In order to fabricate the PMOSFET semiconductor structure, a mask is applied to a semiconductor substrate for the definition of a window delimited by a peripheral edge. An N-doped well is thereupon produced in the P-doped semiconductor substrate by means of high-voltage ion implantation through the window delimited by the mask, the edge zone of said N-doped well reaching as far as the surface of the semiconductor substrate. The individual regions for the source, drain and bulk of the PMOSFET semiconductor structure are then produced in the P-doped inner zone enclosed by the well. The P-doped inner zone forms the drift zone of the PMOSFET structure. Since the drift zone has the weak basic doping of the substrate, the PMOSFET has a high dielectric strength.

Abstract: The invention relates to a cabin pressure control system (10), a method of controlling the actual pressure inside a cabin (50) and an outflow valve (14; 15; 16; 17), especially for use in said system (10) or said method. The invention provides communication of actual cabin pressure to the outflow valve (14; 15; 16; 17) and additionally a common data exchange line (22) connecting the components of the cabin pressure control system (10). The system (10) is highly redundant and reliable, guarantees the desired sophisticated pressure control even if one or several components fail and allows complete elimination of the previously used fully pneumatic safety valves.

Abstract: The invention relates to a cabin pressure control system (10), a method of controlling the actual pressure inside a cabin (50) and an outflow valve (14; 15; 16; 17), especially for use in said system (10) or said method. The invention provides communication of actual cabin pressure to the outflow valve (14; 15; 16; 17) and additionally a common data exchange line (22) connecting the components of the cabin pressure control system (10). The system (10) is highly redundant and reliable, guarantees the desired sophisticated pressure control even if one or several components fail and allows complete elimination of the previously used fully pneumatic safety valves.

Abstract: Procedure and device for cleaning disk-shaped objects, in particular wafers, with sonification and water as rinsing medium and coupling liquid between the ultrasonic transmitter and the surface which is to be cleaned, whereby the wafer is preferentially held by vacuum suction on a rotating plate and the radiating surface of an ultrasonic transmitter is approached to the surface which is to be cleaned to within a distance in the millimeter range and a flowing film of ultra-pure water is produced between the disk surface and the radiating transmitter surface. The particles dislodged from the disk surface by the sonification are carried away by the flowing water and ejected radially with the water by rotating the disk. The ejected water impinges on the sidewalls of a trough and is drained away without splashing.

Abstract: The circuit for feeding a Wheatstone Bridge (DMS 1 . . . DMS 4) with a rectangular waveform alternating voltage which is derived from a single DC reference voltage, consists of a first operational amplifier (V 1) whose positive input is connected to the DC reference voltage and whose negative input is connected via the switches (S 5 and S 6) alternately to the one (A) or to the other (B) feed point of the bridge, and a second operational amplifier (V 2) whose positive input is connected to ground potential and whose negative input is connected to one measuring input (C) of the bridge. The outputs of the two operational amplifiers (V 1 and V 2) are connected via the switches (S 1 . . . S 4) alternately to the one (A) and to the other (B) feed point of the bridge, and the output signal is taken off at the second measuring output (D) of the bridge.

Abstract: A technique for handling discs, such as wafers for integrated circuits, which must be processed in ultra-clean rooms and which are transported to various workstations for processing. A horizontally extended rail has storage positions therealong where standard commercial carriers are positioned which contain vertically standing wafers. A lifting device can lift any carrier over neighboring carriers and moves it to a carrying basket located on an extension of the rail. The carrying basket is then turned by 90.degree. so that the vertical wafers lie horizontally. A tongue-shaped device can be moved under any of these wafers for removal thereof from the basket and subsequent transport to a workstation, and return.

Abstract: A technique for handling discs, such as wafers for integrated circuits, which must be processed in ultra-clean rooms and which are transported to various workstations for processing. A horizontally extended rail has storage positions therealong where standard commercial carriers are positioned which contain vertically standing wafers. A lifting device can lift any carrier over neighboring carriers and moves it to a carrying basket located on an extension of the rail. The carrying basket is then turned by 90.degree. so that the vertical wafers lie horizontally. A tongue-shaped device can be moved under any of these wafers for removal thereof from the basket and subsequent transport to a workstation, and return.

Abstract: A method of fabricating a semiconductor device. A series of layers is deposited on a semiconductor substrate of a first conductivity type to form a shielding arrangement, including an upper part and a lower part, to provide a shield against accelerated ions. This is followed by forming openings in the shielding arrangement by microlithographic processes and anisotropic etching, and then implanting ions via the openings to form one of a base area and a base-connection area of the first conductivity type. Edges of the openings are displaced by isotropic etching of the lower part of the shielding arrangement.

Abstract: An analog-to-digital converter operates according to the multiple ramp procedure with continuous integration of the input signal in a charge storage or charge summation circuit, whereby downward integration is performed at periodically recurrent time intervals with the aid of a comparator circuit at the output of the charge storage or charge summation circuit, a logic circuit, a clock oscillator, a switching circuit, a first reference signal and a second reference signal. Hereby the duration of the switched-on state of one of the reference signals is a measure for the input signal. The transfer function of the quantization noise H.sub.q (z) with an n-th order (n=1,2,3, . . . ) high pass filter characteristic can be derived from a transfer function H(z) describing the specified configuration.

Abstract: Integrating analog to digital converter operating according to a multiple ramp procedure and having a charge storage or charge summation circuit which continuously up-integrates an input signal and which by means of a following comparator, a logic circuit and reference currents or reference voltages, down-integrates during periodically recurrent time intervals, the instants being defined by an oscillator, a timebase counter and a bistable stage. The time between two successive such instants being called a submeasurement. At the imput of the charge storage or charge summation circuit used for the input signal or at one its other inputs, convergence accelerating signals are superimposed after every nth (n=1,2,3, . . . ) submeasurement to provide for strongly enhanced convergence range and for shorter convergence period, and these convergence accelerating signals having Taylor series expansions according to time in the time interval of a submeasurement which are first or higher order polynomials.

Abstract: Apparatus for measuring weight and force has a load reception part arranged for deflection on a fixed part of a weighing and force-measuring system and includes a compensation coil arrangement situated in a constant magnetic field. At least one position sensor ascertains load-dependent deflections of the load reception part from a predetermined position and feeds a sensor signal to an electric regulator circuit. The regulator circuit regulates the current through the compensation coil arrangement so that the load reception part is returned to its predetermined position. The regulator circuit includes means which impart, alternately, positive and negative values, determined by the loading, to the current flowing through the compensation coil arrangement.

Abstract: An analog current I.sub.1, to be digitized is fed continuously to the input of an integrator. Two pulse counters, serially connected, algebraically count pulses from a pulse generator, the first pulse counter of the two setting, upon overflow, a bistable element to one of its states. The bistable element will remain in the state until the first pulse of the pulse generator, after the next change-over of the threshold switch occurs. In accordance with the state of the threshold switch, the bistable flip-flop circuit permits either a current I.sub.2, or a current I.sub.3 (the two currents being of opposite polarity) to be applied, simultaneously with the current I.sub.1, to the integrator by suitable switches during predetermined time intervals W. The time interval W is defined as the sum of the timing intervals occurring between two successive overflow pulses of the second counter during which I.sub.2 is simultaneously integrated with current I.sub.