Abstract: A printing process for a metal container includes the steps: Heating the metal container, in particular formed as a metal bottle ready for filling, to a pre-treatment temperature lying in an interval between 100 degrees Celsius and 250 degrees Celsius, cooling the metal container to a temperature below 100 degrees Celsius, locally activating a printing zone, formed on an outer surface of the metal container to increase a surface energy of the printing zone and/or locally heating the printing zone to a printing temperature which is in an interval between 30 degrees Celsius and 70 degrees Celsius, printing the printing zone with a printing method.

Abstract: A method of splitting off a semiconductor wafer from a semiconductor bottle includes: forming a separation region within the semiconductor boule, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor boule; and applying an external force to the semiconductor boule such that at least one crack propagates along the separation region and a wafer splits from the semiconductor boule.

Abstract: A method of processing a semiconductor wafer includes: forming one or more epitaxial layers over a first main surface of the semiconductor wafer; forming one or more porous layers in the semiconductor wafer or in the one or more epitaxial layers, wherein the semiconductor wafer, the one or more epitaxial layers and the one or more porous layers collectively form a substrate; forming doped regions of a semiconductor device in the one or more epitaxial layers; and after forming the doped regions of the semiconductor device, separating a non-porous part of the semiconductor wafer from a remainder of the substrate along the one or more porous layers.

Abstract: A power semiconductor device includes a semiconductor body having a front side surface, and a first passivation layer arranged above the front side surface. The first passivation layer is a polycrystalline diamond layer.

Abstract: A method includes: providing a layer of porous silicon carbide supported by a silicon carbide substrate; providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide; forming semiconductor devices in the layer of epitaxial silicon carbide; and separating the silicon carbide substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. The layer of porous silicon carbide includes dopants defining a resistivity of the layer of porous silicon carbide. The resistivity of the layer of porous silicon carbide is different from a resistivity of the silicon carbide substrate. Additional methods are described.

Abstract: A method of manufacturing semiconductor devices in a silicon MCZ (magnetic Czochralski) semiconductor body is proposed. The method includes processing the silicon MCZ semiconductor body by an oxidation process at temperatures exceeding 1150° C. and below 1220° C. Thereafter, platinum (Pt) is introduced into the silicon MCZ semiconductor body.

Abstract: A power semiconductor diode includes: a semiconductor body with a drift region of a first conductivity type; a first load terminal at a first side of the semiconductor body coupled to an anode region of a second conductivity type in the semiconductor body and coupled to the drift region; a second load terminal at a second side of the semiconductor body coupled to both cathode regions of the first conductivity type and short regions of the second conductivity type of a doped region in the semiconductor body and coupled to the drift region; and a resistive element external of the semiconductor body. The diode conducts a load current between the load terminals, a first path of which crosses the anode region, drift region and cathode regions and a second path of which crosses the anode region, drift region and short regions. The resistive element exhibits a resistance having a positive-temperature-coefficient.

Abstract: A power semiconductor device includes: a semiconductor body that conducts a load current between first and second load terminals at opposite first and second sides; a drift region of a first conductivity type; trenches extending from the first side towards the second side and each including a trench electrode; mesas laterally confined by the trenches and each including first and second type mesas; and semiconductor structures each including a serial connection of a first region of the first conductivity type coupled to or formed by the drift region, a second region of a second conductivity type and a third region of the first conductivity type coupled to the first load terminal by at least one of a first ohmic resistor and a Zener diode. Each first type mesa is electrically connected to the first load terminal and devoid of the semiconductor structures which are arranged in the second type mesas.

Abstract: pa The method of processing a semiconductor wafer includes forming one or more epitaxial layers over its first main surface. It also involves forming one or more porous layers within the semiconductor wafer or within the epitaxial layers. Together, the semiconductor wafer, the epitaxial layer(s), and the porous layer(s) form a substrate. Next, doped regions of a semiconductor device are formed within the epitaxial layer(s). After forming these doped regions, a non-porous part of the semiconductor wafer is separated from the rest of the substrate along the porous layer(s).

Abstract: A power semiconductor device includes, an active area that conducts load current between first and second load terminal structures, a drift region, and a backside region that includes, inside the active area, first and second backside emitter zones one or both of which includes: first sectors having at least one first region of a second conductivity type contacting the second load terminal structure and a smallest lateral extension of at most 50 ?m; and/or second sectors having a second region of the second conductivity type contacting the second load terminal structure and a smallest lateral extension of at least 50 ?m. The emitter zones differ by at least of: the presence of first and/or second sectors; smallest lateral extension of first and/or second sectors; lateral distance between neighboring first and/or second sectors; smallest lateral extension of the first regions; lateral distance between neighboring first regions within the same first sector.

Abstract: A method of manufacturing a vertical power semiconductor device includes forming a drift region in a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction, the drift region including platinum atoms, and forming a field stop region in the semiconductor body between the drift region and the second main surface, the field stop region including a plurality of impurity peaks, wherein a first impurity peak of the plurality of impurity peaks is set a larger concentration than a second impurity peak of the plurality of impurity peaks, wherein the first impurity peak includes hydrogen and the second impurity peak includes helium.

Abstract: A method of forming a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate; increasing the porosity of the first semiconductor layer; first annealing the first semiconductor layer in an atmosphere including an inert gas; forming a second semiconductor layer on the first semiconductor layer; and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer. Additional methods of forming a semiconductor device are described.

Abstract: A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.

Abstract: A method of manufacturing a semiconductor device includes forming a doped region in a semiconductor body. Forming the doped region includes: introducing first dopants through a first surface of the semiconductor body at a first vertical reference level by a first ion implantation process; thereafter, applying a first heat treatment to the semiconductor body; and thereafter, introducing second dopants through the first surface of the semiconductor body at the first vertical reference level by a second ion implantation process. An atomic number of the first dopants is equal to an atomic number of the second dopants. An ion implantation energy of the second ion implantation process differs by less than 20% from an ion implantation energy of the first ion implantation process. An ion implantation dose of the second ion implantation process differs by less than 20% from an ion implantation dose of the first ion implantation process.

Abstract: In order to improve the mechanical stability of an X-ray grating with top bridges for X-ray dark field imaging and/or X-ray phase contrast imaging, it is proposed to reduce or prevent the undesired high stress on the top bridges by a change in the manufacturing process. Specifically, it is proposed to electroplate the top bridges after the bending. In other words, the electroplating of the top bridges is performed on the bent geometry.

Abstract: A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SIC) semiconductor body including a trench structure. The trench structure extends into the SiC semiconductor body at a first surface of the SiC semiconductor body. The trench structure includes a gate electrode and a gate dielectric arranged between the gate electrode and the SiC semiconductor body. An interlayer dielectric structure is arranged on the trench structure. The interlayer dielectric structure includes at least one of an aluminum nitride layer, a silicon nitride layer, an aluminum oxide layer, or a boron nitride layer. The vertical power semiconductor device further includes a source or emitter electrode on the interlayer dielectric structure.

Abstract: A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.

Abstract: A semiconductor device includes a semiconductor substrate having a first dopant and a second dopant. A covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than the covalent atomic radius of the second dopant. The semiconductor device further includes a semiconductor layer on the semiconductor substrate and semiconductor device elements in the semiconductor layer. A vertical concentration profile of the first dopant decreases along at least 80% of a distance between an interface of the semiconductor substrate and the semiconductor layer to a surface of the semiconductor substrate opposite to the interface.

Abstract: A method of producing a semiconductor device includes forming a plurality of transistor cells in a SiC substrate and electrically connected in parallel to form a transistor having a specified operating temperature range. Forming each transistor cell includes forming a gate structure having a gate electrode, and a gate dielectric stack separating the gate electrode from the SiC substrate and including a ferroelectric insulator. The method further includes doping the ferroelectric insulator with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor.

Abstract: A semiconductor device includes a silicon carbide (SiC) drift zone over a SiC field stop zone and/or a SiC semiconductor substrate. A concentration of Z1/2 defects in the SiC drift zone is at least one order of magnitude smaller than in the SiC field stop zone and/or the SiC semiconductor substrate. Separately or in combination, a concentration of Z1/2 defects in a part of the SiC drift zone is at least one order of magnitude smaller than in another part of the drift zone.