Patents by Inventor Joachim Schulze

Joachim Schulze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220367191
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Inventors: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 11502190
    Abstract: A vertical power semiconductor device is described. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface. A thickness of the semiconductor body between the first main surface and the second main surface ranges from 40 ?m to 200 ?m. Active device elements are formed in the semiconductor body at the first main surface. Edge termination elements at least partly surround the active device elements at the first main surface. A diffusion region extends into the semiconductor body from the second main surface. A doping concentration profile of the diffusion region decreases from a peak concentration Ns at the second main surface to a concentration Ns/e, e being Euler's number, over a vertical distance ranging from 1 ?m to 5 ?m.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: November 15, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Andre Brockmeier, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Publication number: 20220359194
    Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Iris MODER, Bernhard GOLLER, Tobias Franz Wolfgang HOECHBAUER, Roland RUPP, Francisco Javier SANTOS RODRIGUEZ, Hans-Joachim SCHULZE
  • Publication number: 20220359428
    Abstract: A method for processing a semiconductor wafer is proposed. The method may include: reducing a thickness of the semiconductor wafer; before or after reducing the thickness of the semiconductor wafer, placing a carrier structure at a first side of the semiconductor wafer; and after reducing the thickness of the semiconductor wafer, providing a support structure at a second side of the semiconductor wafer opposite to the first side. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Francisco Javier Santos Rodriguez, Alexander Breymesser, Erich Griebl, Michael Knabl, Matthias Kuenle, Andreas Moser, Roland Rupp, Hans-Joachim Schulze, Sokratis Sgouridis, Stephan Voss
  • Patent number: 11476111
    Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 18, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Iris Moder, Bernhard Goller, Tobias Franz Wolfgang Hoechbauer, Roland Rupp, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Publication number: 20220289659
    Abstract: The present invention is related to a method for the production of a dicarboxylic acid, wherein the method comprises a bioconversion step, wherein in the bioconversion step, the dicarboxylic acid is produced from a precursor compound contained in a medium; and a purification step for purifying the dicarboxylic acid from the medium, wherein the purification step comprises (a) a nano-diafiltration step and/or (b) a distillation step or an evaporation step or both a distillation step and an evaporation step, wherein preferably if the purification step comprises (a) the nano-diafiltration step and (b) the distillation step or the evaporation step or both the distillation step and the evaporation step, the nano-diafiltration step is carried out prior to the distillation step and the evaporation step, respectively, and wherein the dicarboxylic acid is selected from the group comprising decanedioic acid, dodecanedioic acid, tetradecanedioic acid and hexadecanedioic acid, preferably the dicarboxylic acid is dodec
    Type: Application
    Filed: May 18, 2022
    Publication date: September 15, 2022
    Inventor: Joachim SCHULZE
  • Patent number: 11437470
    Abstract: The disclosure relates to a semiconductor component having an SiC semiconductor body and a first load terminal on a first surface of the SiC semiconductor body. A second load terminal is formed on a second surface of the SiC semiconductor body opposite the first surface. The semiconductor component has a drift zone of a first conductivity type in the SiC semiconductor body and a first semiconductor area of a second conductivity type which is electrically connected to the first load terminal. A pn junction between the drift zone and the first semiconductor area defines a voltage blocking strength of the semiconductor component.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: September 6, 2022
    Assignee: Infineon Technologies AG
    Inventors: Thomas Basler, Rudolf Elpelt, Hans-Joachim Schulze
  • Patent number: 11437471
    Abstract: A power semiconductor device includes: a semiconductor body; a first load terminal structure coupled to the body front side and a second load terminal structure coupled to the body backside; an active area for conducting a load current between the load terminal structures; a drift region having a first conductivity type; a backside region arranged at the backside and including, inside the active area, first and second backside emitter zones. At least one of the backside emitter zones includes: first sectors each having at least one first region of a second conductivity type, the first region arranged in contact with the second load terminal structure and having a smallest lateral extension of at most 50 ?m; and/or second sectors each having a second region of the second conductivity type arranged in contact with the second load terminal structure and having a smallest lateral extension of at least 50 ?m.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: September 6, 2022
    Assignee: Infineon Technologies AG
    Inventors: Roman Baburske, Moritz Hauf, Hans-Joachim Schulze, Holger Schulze, Benedikt Stoib
  • Patent number: 11417528
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 16, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze
  • Publication number: 20220246744
    Abstract: A transistor device is provided. In an example, the transistor device includes a semiconductor body having a first main surface, a second main surface opposite to the first main surface. The transistor device further includes a transistor cell array including a plurality of transistor cells. The transistor cell array includes a first load electrode over the first main surface. The first load electrode is electrically connected to the plurality of transistor cells. The transistor cell array further includes a second load electrode over the second main surface. The second load electrode is electrically connected to the plurality of transistor cells. The plurality of transistor cells includes at least one control electrode including carbon.
    Type: Application
    Filed: February 1, 2022
    Publication date: August 4, 2022
    Inventors: Ralf Siemieniec, Ingo Muri, Till Schloesser, Hans-Joachim Schulze, Olaf Storbeck
  • Publication number: 20220246745
    Abstract: A silicon carbide device includes a semiconductor substrate comprising a body region and transistor cell that comprises a source region, and a titanium carbide field electrode of the transistor cell, wherein the titanium carbide field electrode is connected to a reference voltage metallization structure or connectable to the reference voltage metallization structure by a switching device, wherein the reference voltage metallization is connected to a fixed voltage that is independent from a gate voltage of the transistor cell.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Inventors: Ralf Siemieniec, Thomas Aichinger, Iris Moder, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Carsten von Koblinski
  • Patent number: 11394194
    Abstract: A power inverter includes a bridge circuit including a first half-bridge and a second half-bridge, each half-bridge including a high-side device and a low-side device, and a gate driver circuit connected with each gate of the high-side device and low-side power device of the first and second half-bridges and operable to provide each gate with a respective voltage to control operation of the respective power device. The gate driver is operable to provide a first voltage which is higher than a first threshold voltage of the respective power device, and a second voltage which is higher than a surge threshold of the respective power device. The surge threshold is higher than the first threshold and defines the onset of a surge current operation area of the respective power device at which the power device becomes conducts a surge current that is larger than the rated current of the device.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: July 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Thomas Basler, Hans-Joachim Schulze
  • Publication number: 20220199800
    Abstract: A semiconductor device includes a silicon carbide (SiC) drift zone over a SiC field stop zone and/or a SiC semiconductor substrate. A concentration of Z1/2 defects in the SiC drift zone is at least one order of magnitude smaller than in the SiC field stop zone and/or the SiC semiconductor substrate. Separately or in combination, a concentration of Z1/2 defects in a part of the SiC drift zone is at least one order of magnitude smaller than in another part of the drift zone.
    Type: Application
    Filed: March 10, 2022
    Publication date: June 23, 2022
    Inventors: Hans-Joachim Schulze, Jens Peter Konrath, Andre Rainer Stegner, Helmut Strack
  • Patent number: 11342433
    Abstract: A silicon carbide device includes a silicon carbide substrate having a body region and a source region of a transistor cell. Further, the silicon carbide device includes a titanium carbide gate electrode of the transistor cell.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 24, 2022
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Thomas Aichinger, Iris Moder, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Carsten von Koblinski
  • Patent number: 11342187
    Abstract: Forming a semiconductor arrangement includes providing a first semiconductor layer having a first surface, forming a first plurality of trenches in the first surface of the first semiconductor layer, each of the trenches in the first plurality having first and second sidewalls that extend from the first surface to a bottom of the respective trench, implanting first type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, implanting second type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, and annealing the semiconductor arrangement to simultaneously activate the first type dopant atoms and the second type dopant atoms.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: May 24, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Hans Weber, Franz Hirler, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
  • Publication number: 20220149038
    Abstract: A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 12, 2022
    Inventors: Edward Fuergut, Peter Friedrichs, Ralf Otremba, Hans-Joachim Schulze
  • Publication number: 20220149156
    Abstract: A semiconductor device includes: a silicon carbide semiconductor body having a source region of a first conductivity type and a body region of a second conductivity type; and a trench structure extending from a first surface into the silicon carbide semiconductor body along a vertical direction, the trench structure having a gate electrode and a gate dielectric. The trench structure is stripe-shaped and runs along a longitudinal direction that is perpendicular to the vertical direction. The source region includes a first source sub-region and a second source sub-region alternately arranged along the longitudinal direction. A doping concentration profile of the first source sub-region along the vertical direction differs from a doping concentration profile of the second source sub-region along the vertical direction. A corresponding method of manufacturing the semiconductor device is also described.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Inventors: Thomas Basler, Caspar Leendertz, Hans-Joachim Schulze
  • Patent number: 11315892
    Abstract: A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: April 26, 2022
    Inventors: Roman Roth, Frank Hille, Hans-Joachim Schulze
  • Patent number: 11309410
    Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive trench of the device for the same gate potential condition.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: April 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
  • Patent number: 11302795
    Abstract: A method of manufacturing a semiconductor device is proposed. A silicon carbide, SiC, semiconductor body is provided. Ions are introduced into the SiC semiconductor body through a first surface of the SiC semiconductor body by at least one ion implantation process. Thereafter, a SiC device layer is formed on the first surface of the SiC semiconductor body. Semiconductor device elements are formed in or over the SiC device layer.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: April 12, 2022
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Jens Peter Konrath, Andre Rainer Stegner, Helmut Strack