Abstract: A semiconductor product, including: a base region doped with a first conductivity type; a plurality of stripe regions doped with a second conductivity type, provided on an upper surface of the base region, and the second conductivity type is different from the first conductivity type; a plurality of cell regions doped with the second conductivity type, provided on the upper surface of the base region; and a metal layer arranged on the upper surface of the base region, so that the metal layer defines a Schottky barrier with the base region and covers the plurality of stripe regions and the plurality of cell regions; and each cell region of a majority of the plurality of cell regions contacts at least one neighboring stripe region of the plurality of stripe regions and the stripe regions and the cell regions extend into the base region to different depths.

Abstract: The present disclosure relates to a wide band-gap merged p-i-n/Schottky, MPS, diode, and to a method of manufacturing the same. The present disclosure particularly relates to Silicon Carbide, SiC, MPS diodes. According to the present disclosure, the MPS diode includes different Schottky contacts with different IV characteristics, and/or ohmic contacts with a different contact resistance and/or threshold voltage. This allows the conduction area of the MPS diode to change more gradually with forward bias thereby avoiding drawbacks associated with a large conduction area when switching from a forward biasing mode to a reverse biasing mode. Therefore, the dynamic switching performance can be improved in a wide operation voltage range.

Abstract: The semiconductor device (100) comprises at least one semiconductor element (20), a metallization structure comprising a first (31) and a second line (32) and extending thereon a resistor. An electrically insulating protection layer (36) is present on the resistor (35) and is defined in a pattern that is substantially identical to the resistor pattern and has a temperature stability up to a temperature that is at least equal to a deposition temperature of a passivation layer (37) to be deposited thereon so as to cover the metallization structure. Both the resistor (35) and the protection layer (36) are deposited conformally on the metallization structure and any underlying substrate.

Abstract: The semiconductor device (100) comprises at least one semiconductor element (20), a metallization structure comprising a first (31) and a second line (32) and extending thereon a resistor. An electrically insulating protection layer (36) is present on the resistor (35) and is defined in a pattern that is substantially identical to the resistor pattern and has a temperature stability up to a temperature that is at least equal to a deposition temperature of a passivation layer (37) to be deposited thereon so as to cover the metallization structure. Both the resistor (35) and the protection layer (36) are deposited conformally on the metallization structure and any underlying substrate.