Patents by Inventor Joachim von Buttlar

Joachim von Buttlar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11934220
    Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: March 19, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eberhard Engler, Dan F. Greiner, Michel H. T. Hack, Timothy J. Slegel, Joachim von Buttlar
  • Patent number: 11734013
    Abstract: An exception summary is provided for an invalid value detected during instruction execution. An indication that a value determined to be invalid was included in input data to a computation of one or more computations or in output data resulting from the one or more computations is obtained. The value is determined to be invalid due to one exception of a plurality of exceptions. Based on obtaining the indication that the value is determined to be invalid, a summary indicator is set. The summary indicator represents the plurality of exceptions collectively.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: August 22, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Laith M. AlBarakat, Jonathan D. Bradbury, Timothy Slegel, Cedric Lichtenau, Joachim von Buttlar
  • Publication number: 20220413867
    Abstract: An exception summary is provided for an invalid value detected during instruction execution. An indication that a value determined to be invalid was included in input data to a computation of one or more computations or in output data resulting from the one or more computations is obtained. The value is determined to be invalid due to one exception of a plurality of exceptions. Based on obtaining the indication that the value is determined to be invalid, a summary indicator is set. The summary indicator represents the plurality of exceptions collectively.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 29, 2022
    Inventors: Laith M. AlBarakat, Jonathan D. Bradbury, Timothy Slegel, Cedric Lichtenau, Joachim von Buttlar
  • Patent number: 11444843
    Abstract: A computer-implemented method for simulating a system of at least two computing systems connected via at least one data packet connection, wherein a computing system comprises interconnect adapters for physical connections based on a physical layer protocol each. A packet switching component is provided, as are physical attachments for each interconnect adapter. The physical attachments are registered. A connection director is provided for managing the data packet exchange. In response to the receipt of a simulation start indicator, each physical attachment registers its unique address at the package switching component. This assigns unique identifiers for each computing system, and unique identifiers for simulated physical layer protocols.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: September 13, 2022
    Assignee: International Business Machines Corporation
    Inventors: Carsten Otte, Georg Drache, Joachim von Buttlar, Jens Mehler, Sebastian Stork
  • Patent number: 11269632
    Abstract: An instruction to convert data from a source data type to a target data type is obtained. The source data type is selected from one or more source data types supported by the instruction, and the target data type is selected from one or more target data types supported by the instruction. Based on a selected data type of the source data type or the target data type, a determination is made of a rounding mode for use by the instruction. The rounding mode is implicitly set based on the selected data type; it is assigned to the selected data type. A conversion of the data from the source data type to the target data type is performed. The conversion includes performing a rounding operation using the rounding mode implicitly set. The performing the conversion provides a result in the target data type, which is written to a select location.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: March 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Laith M. AlBarakat, Jonathan D. Bradbury, Timothy Slegel, Cedric Lichtenau, Joachim von Buttlar
  • Publication number: 20220035399
    Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.
    Type: Application
    Filed: October 20, 2021
    Publication date: February 3, 2022
    Inventors: Eberhard Engler, Dan F. Greiner, Michel H. T. Hack, Timothy J. Slegel, Joachim von Buttlar
  • Patent number: 11199870
    Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: December 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eberhard Engler, Dan F. Greiner, Michel H. T. Hack, Timothy J. Slegel, Joachim von Buttlar
  • Publication number: 20210168041
    Abstract: A computer-implemented method for simulating a system of at least two computing systems connected via at least one data packet connection, wherein a computing system comprises interconnect adapters for physical connections based on a physical layer protocol each. A packet switching component is provided, as are physical attachments for each interconnect adapter. The physical attachments are registered. A connection director is provided for managing the data packet exchange. In response to the receipt of a simulation start indicator, each physical attachment registers its unique address at the package switching component. This assigns unique identifiers for each computing system, and unique identifiers for simulated physical layer protocols.
    Type: Application
    Filed: December 3, 2019
    Publication date: June 3, 2021
    Inventors: Carsten Otte, Georg Drache, Joachim von Buttlar, Jens Mehler, Sebastian Stork
  • Publication number: 20190377379
    Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.
    Type: Application
    Filed: August 19, 2019
    Publication date: December 12, 2019
    Inventors: Eberhard Engler, Dan F. Greiner, Michel H. T. Hack, Timothy J. Slegel, Joachim von Buttlar
  • Patent number: 10423191
    Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eberhard Engler, Dan F. Greiner, Michel H. T. Hack, Timothy J. Slegel, Joachim von Buttlar
  • Publication number: 20180203480
    Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.
    Type: Application
    Filed: January 19, 2017
    Publication date: July 19, 2018
    Inventors: Eberhard Engler, Dan F. Greiner, Michel H. T. Hack, Timothy J. Slegel, Joachim von Buttlar
  • Patent number: 9135004
    Abstract: A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is ‘1’, in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: September 15, 2015
    Assignee: International Business Machines Corporation
    Inventors: Dan F. Greiner, Timothy J. Slegel, Joachim von Buttlar
  • Publication number: 20150006860
    Abstract: A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is ‘1’, in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register.
    Type: Application
    Filed: September 12, 2014
    Publication date: January 1, 2015
    Inventors: Dan F. Greiner, Timothy J. Slegel, Joachim von Buttlar
  • Patent number: 8838943
    Abstract: A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is ‘1’, in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dan F. Greiner, Timothy J. Slegel, Joachim von Buttlar
  • Publication number: 20120246508
    Abstract: A method is presented for continuously providing a high precision system clock associated with a processing core, wherein the system clock includes a host clock register that is incremented via a high precision oscillator, the method includes: providing a firmware clock register, incrementing the firmware clock register based on the host clock register being incremented, monitoring for failures of the host clock register, and during a failure of the host clock register continuously incrementing the firmware clock register by means of timing signals of the processing core, and upon receipt of a request to provide a clock value, providing the content of the host clock register if no failure was detected, or if failure was detected, providing the content of the firmware clock register.
    Type: Application
    Filed: February 15, 2012
    Publication date: September 27, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eberhard ENGLER, Guenter GERWIG, Frank LEHNERT, Klaus MEISSNER, Joachim von BUTTLAR
  • Patent number: 7996585
    Abstract: Disclosed are a method and system of tracking real time use of I/O control blocks on a processing unit basis, in a multiprocessing system, such that in the case of a processing unit failure, a list accurately and concisely identifies the control blocks that need to be recovered. This eliminates the need to scan all the I/O control blocks, greatly reducing the overall system recovery time and minimizing impact to the rest of the running system. The preferred embodiment of the invention uses a task control block structure to record which I/O control blocks are in use by each Processing Unit. Also, the lock word structure defined in the I/O control blocks is provided with an index back into the task control block to facilitate managing the task control block entries.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: August 9, 2011
    Assignee: International Business Machines Corporation
    Inventors: Janet R. Easton, Elke Nass, Kenneth J. Oakes, Andrew W. Piechowski, Martin Taubert, John S. Trotter, Ambrose Verdibello, Joachim von Buttlar, Robert Whalen, Jr.
  • Patent number: 7895419
    Abstract: A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is ‘1’, in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Dan F. Greiner, Timothy J. Slegel, Joachim von Buttlar
  • Publication number: 20100299506
    Abstract: A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is ‘1’, in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register.
    Type: Application
    Filed: July 21, 2010
    Publication date: November 25, 2010
    Applicant: International Business Machines Corporation
    Inventors: Dan F. Greiner, Timothy J. Slegel, Joachim von Buttlar
  • Patent number: 7752497
    Abstract: Disclosed are a method and system for detecting errors in a computer system including a processing unit to perform tasks to change items. The method comprises the steps of assigning a task control block to the processing unit, and using the task control block to keep track of items being changed by the processing unit. The method comprises the further steps of at defined times, checking the task control block to identify items being changed by the processing unit, and checking the states of said identified items to determine if those states are correct. The preferred embodiment of the invention detects an error when it arises (where possible), and utilizes an infrastructure that allows simple and periodic consistency checks (for example, at designated code points) that detect the error before it causes follow-on problems.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Joachim von Buttlar, Janet R. Easton, Kenneth J. Oakes, Andrew W. Piechowski, Martin Taubert, John S. Trotter
  • Publication number: 20090182982
    Abstract: A rotate then operate instruction having a Z bit is fetched and executed wherein a first operand in a first register is rotated by an amount. If the Z bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the Z bit is ‘1’, in addition to the inserted bits bits other than the inserted bits of the second operand are set to zeros.
    Type: Application
    Filed: January 11, 2008
    Publication date: July 16, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Timothy J. Slegel, Joachim von Buttlar