Abstract: The present invention relates to a gate structure and a method for its production. In particular, the present invention relates to agate structuring of a field effect transistor (FET), wherein the field effect transistor with the same active layer can be constructed as a depletion type, or D-type, as an enhancement type, or E-type, and as a low noise type, or LN-type, on a shared substrate base using a uniform method.

Abstract: The invention relates to a method for producing a transistor with a high degree of electron mobility and to a transistor with a high degree of electron mobility. The method is characterized in that an epitaxial layer is first grown on a flat substrate, and the flat substrate is then completely removed from the bottom of the epitaxial layer, wherein a thermally conductive layer is applied onto the bottom of the epitaxial layer such that the thermally conductive layer contacts at least 80%, preferably at least 90%, particularly preferably at least 95%, in particular 100%, of the bottom of the epitaxial layer. The method is simple and inexpensive to carry out and provides a transistor which has a high degree of electron mobility, an improved electric output without backgating, and an improved heat dissipation. The method additionally allows a transistor to be provided with a vertical transistor structure.

Abstract: This invention concerns a gate structure and a process for its manufacturing. In particular, the present invention concerns the gate structuring of a field effect transistor with reduced thermo-mechanical stress and increased reliability (lower electromigration or diffusion of the gate metal). The gate structure according to the invention comprises a substrate; an active layer disposed on the substrate; an intermediate layer disposed on the active layer, the intermediate layer-having a recess extending through the entire intermediate layer towards the active layer; and a contact element which is arranged within the recess, the contact element completely filling the recess and extending to above the intermediate layer, the contact element resting at least in sections directly on the intermediate layer; the contact element being made of a Schottky metal and the contact element having an interior cavity completely enclosed by the Schottky metal.

Abstract: The present invention relates to a gate structure and a method for its production. In particular, the present invention relates to a gate structuring of a field effect transistor (FET), wherein the field effect transistor with the same active layer can be constructed as a depletion type, or D-type, as an enhancement type, or E-type, and as a low noise type, or LN-type, on a shared substrate base using a uniform method.

Abstract: This invention concerns a gate structure and a process for manufacturing. In particular, the present invention concerns the gate structuring of a field effect transistor with reduced thereto-mechanical stress and increased reliability (lower electromigration or diffusion of the gate metal).

Abstract: The invention relates to semiconductor components, in particular to a scalable construction for lateral semiconductor components having high current-carrying capacity. A transistor cell according to the invention comprises a control electrode (203), a plurality of source fields (201) and a plurality of drain fields (202). The control electrode completely encloses at least one of the source fields or drain fields. A transistor according to the invention comprises a plurality of transistor cells on a substrate, each of which comprises a source contact field (206) and/or a drain contact field (207). The source contact fields are conductively connected to each other on the other side of the substrate and the drain contact fields are likewise conductively connected to each other on the other side of the substrate.

Abstract: A transistor in which the electric field is reduced in critical areas using field plates, permitting the electric field to be more uniformly distributed along the component, is provided, wherein the electric field in the active region is smoothed and field peaks are reduced. The semiconductor component has a substrate with an active layer structure, a source contact and a drain contact located on said active layer structure. The source contact and the drain contact are mutually spaced and at least one part of a gate contact is provided on the active layer structure in the region between the source contact and the drain contact, a gate field plate being electrically connected to the gate contact. In addition, at least two separate field plates are placed directly on the active layer structure or directly on a passivation layer.

Abstract: This invention relates to a semiconductor layer structure. The semiconductor layer structure described includes a substrate and a buffer layer deposited onto the substrate. The semiconductor layer structure is characterized in that a drain voltage threshold lower than the breakdown voltage threshold is determined by isolating ions that are selectively implanted in just one region of the substrate into the substrate, wherein charge can dissipate from the one contact through the buffer layer towards a substrate region without isolating ions, if the one potential deviates from the other at least by the drain voltage threshold, and wherein the substrate region without isolating ions is located underneath the one contact. The semiconductor layer structure described allows dissipation of currents induced by induction in blocking active structures without damaging the active structures.

Abstract: The invention relates to a method for producing a metallization for at least one contact pad and a semiconductor wafer having metallization for at least one contact pad. The invention relates to a metallization (and a semiconductor wafer having corresponding metallization) and to a method for the production thereof that first of all can be produced by means of physical gas phase separation (dry separation) and secondly ensures sufficient adhesion of a lot bump.

Abstract: An overvoltage protection device for compound semiconductor field effect transistors includes an implanted region disposed in a compound semiconductor material. The implanted region has spatially distributed trap states which cause the implanted region to become electrically conductive at a threshold voltage. A first contact is connected to the implanted region. A second contact spaced apart from the first contact is also connected to the implanted region. The distance between the first and second contacts partly determines the threshold voltage of the overvoltage protection device.

Abstract: This invention relates to a semiconductor layer structure. The semiconductor layer structure described includes a substrate and a buffer layer deposited onto the substrate. The semiconductor layer structure is characterized in that a drain voltage threshold lower than the breakdown voltage threshold is determined by isolating ions that are selectively implanted in just one region of the substrate into the substrate, wherein charge can dissipate from the one contact through the buffer layer towards a substrate region without isolating ions, if the one potential deviates from the other at least by the drain voltage threshold, and wherein the substrate region without isolating ions is located underneath the one contact. The semiconductor layer structure described allows dissipation of currents induced by induction in blocking active structures without damaging the active structures.

Abstract: The invention relates to a method for producing vertical through-contacts (micro-vias) in semi-conductor wafers in order to produce semi-conductor components, i.e. contacts on the front side of the wafer through the semi-conductor wafer to the rear side of the wafer. The invention also relates to a method which comprises the following steps: blind holes on the contact connection points are laser drilled from the rear side of the wafer into the semi-conductor substrate, the wafer is cleaned, the semi-conductor substrate is plasma etched in a material selected manner until the active layer stack of the wafer is reached, the active layer stack of the wafer is plasma etched in a material selective manner until the contacts, which are to be connected to the rear side of the wafer, are reached, a plating base is applied to the rear side of the wafer and into the blind holes and gold is applied by electrodeposition onto the metallizied rear side of the wafer and the blind holes.

Abstract: The invention relates to semiconductor components, in particular to a scalable construction for lateral semiconductor components having high current-carrying capacity. A transistor cell according to the invention comprises a control electrode (203), a plurality of source fields (201) and a plurality of drain fields (202). The control electrode completely encloses at least one of the source fields or drain fields. A transistor according to the invention comprises a plurality of transistor cells on a substrate, each of which comprises a source contact field (206) and/or a drain contact field (207). The source contact fields are conductively connected to each other on the other side of the substrate and the drain contact fields are likewise conductively connected to each other on the other side of the substrate.

Abstract: The invention relates to a method for producing vertical electrical connections in semiconductor wafers, the method including the following steps: application of a protective resist to the wafer front side; patterning of the protective resist such that the contacts to be connected to the wafer rear side become free; laser drilling of passage holes at the contact connection locations from the wafer rear side through the semiconductor substrate, the active layers and the contacts to be connected on the wafer front side; cleaning of the wafer; application of a plating base to the wafer rear side and into the laser-drilled passage holes; application of gold by electrodeposition onto the metallized wafer rear side and the passage holes; resist stripping of the protective resist; and application of an antiwetting layer in the region of the entrance openings of the passage holes at the wafer rear side.

Abstract: The invention relates to a method for producing a metallization for at least one contact pad and a semiconductor wafer having metallization for at least one contact pad. The invention relates to a metallization (and a semiconductor wafer having corresponding metallization) and to a method for the production thereof that first of all can be produced by means of physical gas phase separation (dry separation) and secondly ensures sufficient adhesion of a lot bump.

Abstract: The invention relates to a transistor, in which the electric field is reduced in critical areas using field plates, thus permitting the electric field to be more uniformly distributed along the component. The aim of the invention is to provide a transistor and a production method therefor, wherein the electric field in the active region is smoothed (and field peaks are reduced), thus allowing the component to be made more simply and cost-effectively. The semiconductor component according to the invention has a substrate (20) which is provided with an active layer structure, a source contact (30) and a drain contact (28) being located on said active layer structure (24, 26). The source contact (30) and the drain contact (28) are mutually spaced and at least one part of a gate contact (32) is provided on the active layer structure (24, 26) in the region between the source contact (30) and the drain contact (28), a gate field plate (34) being electrically connected to the gate contact (32).

Abstract: The invention concerns about electrical devices having improved transfer characteristics and a corresponding method of tailoring the transfer characteristics of such electrical devices. According to one aspect of the invention, there is provided an electrical device including at least two transistor segments or at least two transistors connected in parallel or in series characterized in that the at least two segments of the transistor or the at least two of the transistors have a different single transfer characteristic due to at least one of different topology and different material properties.

Abstract: The invention relates to a method for producing vertical through-contacts (micro-vias) in semi-conductor wafers in order to produce semi-conductor components, i.e. contacts on the front side of the wafer through the semi-conductor wafer to the rear side of the wafer. The invention also relates to a method which comprises the following steps: blind holes on the contact connection points are laser drilled from the rear side of the wafer into the semi-conductor substrate, the wafer is cleaned, the semi-conductor substrate is plasma etched in a material selected manner until the active layer stack of the wafer is reached, the active layer stack of the wafer is plasma etched in a material selective manner until the contacts, which are to be connected to the rear side of the wafer, are reached, a plating base is applied to the rear side of the wafer and into the blind holes and gold is applied by electrodeposition onto the metallizied rear side of the wafer and the blind holes.