Patents by Inventor Joan Josep GINER DE HARO

Joan Josep GINER DE HARO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11890643
    Abstract: A PMUT includes a substrate, a stopper, and a multi-layered structure, where the substrate includes a corner, and a cavity is disposed in the substrate. The stopper is in contact with the corner of the substrate and the cavity. The multi-layered structure is disposed over the cavity and attached to the stopper and the multi-layered structure includes at least one through hole in contact with the cavity.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: February 6, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: You Qian, Joan Josep Giner de Haro, Rakesh Kumar, Jia Jie Xia
  • Patent number: 11785852
    Abstract: A method of forming a microphone device includes: forming a through-hole in a substrate wafer; providing a second wafer; bonding the second wafer to the substrate wafer; and forming a top electrode over a first surface of a single-crystal piezoelectric film of the second wafer. The second wafer may include the single-crystal piezoelectric film. The single-crystal piezoelectric film may have a first surface and an opposing second surface. The second wafer may further include a bottom electrode arranged adjacent to the second surface, and a support member over the single-crystal piezoelectric film. The through-hole in substrate wafer may be at least substantially aligned with at least one of the top electrode and the bottom electrode.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: October 10, 2023
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR SINGAPORE PTE. LTD.
    Inventors: You Qian, Joan Josep Giner De Haro, Rakesh Kumar
  • Patent number: 11706987
    Abstract: A semiconductor device may include: a substrate wafer, a bonding layer at least partially covering a front surface of the substrate wafer, a plurality of silicon pillars bonded to the front surface of the substrate wafer by the bonding layer, a single-crystal piezoelectric film having a first surface and an opposing second surface, a top electrode arranged adjacent to the first surface of the single-crystal piezoelectric film, and a bottom electrode arranged adjacent to the second surface of the single-crystal piezoelectric film. The single-crystal piezoelectric film may be supported by the plurality of silicon pillars such that the second surface of the piezoelectric film and the front surface of the substrate wafer enclose a cavity therebetween.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 18, 2023
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: You Qian, Joan Josep Giner De Haro, Rakesh Kumar
  • Publication number: 20230051656
    Abstract: A method of forming a microphone device includes: forming a through-hole in a substrate wafer; providing a second wafer; bonding the second wafer to the substrate wafer; and forming a top electrode over a first surface of a single-crystal piezoelectric film of the second wafer. The second wafer may include the single-crystal piezoelectric film. The single-crystal piezoelectric film may have a first surface and an opposing second surface. The second wafer may further include a bottom electrode arranged adjacent to the second surface, and a support member over the single-crystal piezoelectric film. The through-hole in substrate wafer may be at least substantially aligned with at least one of the top electrode and the bottom electrode.
    Type: Application
    Filed: November 3, 2022
    Publication date: February 16, 2023
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR SINGAPORE PTE. LTD.
    Inventors: You QIAN, Joan Josep GINER DE HARO, Rakesh KUMAR
  • Patent number: 11527700
    Abstract: A microphone device may include: a substrate wafer, a support member bonded to a front surface of the substrate wafer, a single-crystal piezoelectric film provided over the support member, a top electrode and a bottom electrode. The single-crystal piezoelectric film may have a first surface and an opposing second surface. The top electrode may be arranged adjacent to the first surface of the single-crystal piezoelectric film. The bottom electrode may be arranged adjacent to the second surface of the single-crystal piezoelectric film. The substrate wafer may have a through-hole formed therein. The through-hole of the substrate wafer may be at least substantially aligned with at least one of the top electrode and the bottom electrode.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 13, 2022
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR SINGAPORE PTE. LTD.
    Inventors: You Qian, Joan Josep Giner De Haro, Rakesh Kumar
  • Publication number: 20220048072
    Abstract: A PMUT includes a substrate, a stopper, and a multi-layered structure, where the substrate includes a corner, and a cavity is disposed in the substrate. The stopper is in contact with the corner of the substrate and the cavity. The multi-layered structure is disposed over the cavity and attached to the stopper and the multi-layered structure includes at least one through hole in contact with the cavity.
    Type: Application
    Filed: August 14, 2020
    Publication date: February 17, 2022
    Inventors: You Qian, Joan Josep Giner de Haro, RAKESH KUMAR, Jia Jie Xia
  • Patent number: 11185886
    Abstract: A MEMS device may include a first electrode region; a first piezoelectric layer arranged over the first electrode region; a second electrode region arranged over the first piezoelectric layer; a second piezoelectric layer arranged over the first piezoelectric layer and the second electrode region; a third electrode region arranged over the second piezoelectric layer; a first input port coupled to the first electrode region and/or the second electrode region for providing a first electrical signal to the first piezoelectric layer to generate a first vibration in the first piezoelectric layer; a second input port coupled to the second electrode region and/or the third electrode region for providing a second electrical signal to the second piezoelectric layer to generate a second vibration in the second piezoelectric layer; and an output port configured to receive an output signal including a superposition of the first vibration and the second vibration.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 30, 2021
    Assignee: VANGUARD INIERNATIONAL SEMICONDUCTOR SINGAPORE PTE. LTD.
    Inventors: Humberto Campanella Pineda, Joan Josep Giner De Haro, You Pak-Chum Qian, Rakesh Kumar
  • Publication number: 20210193906
    Abstract: A semiconductor device may include: a substrate wafer, a bonding layer at least partially covering a front surface of the substrate wafer, a plurality of silicon pillars bonded to the front surface of the substrate wafer by the bonding layer, a single-crystal piezoelectric film having a first surface and an opposing second surface, a top electrode arranged adjacent to the first surface of the single-crystal piezoelectric film, and a bottom electrode arranged adjacent to the second surface of the single-crystal piezoelectric film. The single-crystal piezoelectric film may be supported by the plurality of silicon pillars such that the second surface of the piezoelectric film and the front surface of the substrate wafer enclose a cavity therebetween.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 24, 2021
    Inventors: You QIAN, Joan Josep GINER DE HARO, Rakesh KUMAR
  • Publication number: 20210193899
    Abstract: A microphone device may include: a substrate wafer, a support member bonded to a front surface of the substrate wafer, a single-crystal piezoelectric film provided over the support member, a top electrode and a bottom electrode. The single-crystal piezoelectric film may have a first surface and an opposing second surface. The top electrode may be arranged adjacent to the first surface of the single-crystal piezoelectric film. The bottom electrode may be arranged adjacent to the second surface of the single-crystal piezoelectric film. The substrate wafer may have a through-hole formed therein. The through-hole of the substrate wafer may be at least substantially aligned with at least one of the top electrode and the bottom electrode.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 24, 2021
    Inventors: You QIAN, Joan Josep GINER DE HARO, Rakesh KUMAR
  • Patent number: 11016055
    Abstract: Structures for transistor-based sensors and related fabrication methods. A layer stack is formed that includes a semiconductor layer and a cavity. A transistor is formed that has a gate electrode over the layer stack, and an interconnect structure is formed over the layer stack and the transistor. First and second openings are formed that extend through the metallization levels of the interconnect structure and the semiconductor layer to the cavity. The first opening defines a fluid inlet coupled to the cavity, and the second opening defines a fluid outlet coupled to the cavity.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 25, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Humberto Campanella-Pineda, Qizhi Liu, Vibhor Jain, You Qian, Joan Josep Giner de Haro
  • Patent number: 10979019
    Abstract: A resonator device may include a stacked first resonator and second resonator. The first resonator may be configured to resonate at a first operating frequency, and the second resonator may be configured to resonate at a second operating frequency different from the first operating frequency. The first resonator may include a first electrode and a first active layer arranged over the first electrode. The second resonator may include a second active layer arranged over the first active layer, and a second electrode arranged over the second active layer. The stacked first resonator and second resonator may be coupled to a reconfiguration switch for selectively operating at the first operating frequency or the second operating frequency. One of the first resonator and the second resonator is active upon selection by the reconfiguration switch, while the other resonator is inactive.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: April 13, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Joan Josep Giner De Haro, Humberto Campanella Pineda
  • Patent number: 10957787
    Abstract: Transistor-based sensors and fabrication methods for a transistor-based sensor. A semiconductor layer is arranged over a substrate, and an interconnect structure is arranged over the semiconductor layer and the substrate. The semiconductor layer includes first sections composed of a semiconductor material, second sections composed of the semiconductor material, and cavities. The first sections have an alternating arrangement with the second sections in a lateral direction. The semiconductor material of the first sections is polycrystalline, and the semiconductor material of the second sections is single-crystal. First and second openings each extend in a vertical direction through the metallization levels of the interconnect structure to the semiconductor layer or through the substrate to the semiconductor layer. The first opening defines a first fluid inlet coupled to the cavities, and the second opening defines a first fluid outlet coupled to the cavities.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: March 23, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Vibhor Jain, Joan Josep Giner de Haro, Qizhi Liu, You Qian, Humberto Campanella Pineda
  • Publication number: 20210010971
    Abstract: Structures for transistor-based sensors and related fabrication methods. A layer stack is formed that includes a semiconductor layer and a cavity. A transistor is formed that has a gate electrode over the layer stack, and an interconnect structure is formed over the layer stack and the transistor. First and second openings are formed that extend through the metallization levels of the interconnect structure and the semiconductor layer to the cavity. The first opening defines a fluid inlet coupled to the cavity, and the second opening defines a fluid outlet coupled to the cavity.
    Type: Application
    Filed: July 9, 2019
    Publication date: January 14, 2021
    Inventors: Humberto Campanella-Pineda, Qizhi Liu, Vibhor Jain, You Qian, Joan Josep Giner de Haro
  • Publication number: 20200395915
    Abstract: A resonator device may include a stacked first resonator and second resonator. The first resonator may be configured to resonate at a first operating frequency, and the second resonator may be configured to resonate at a second operating frequency different from the first operating frequency. The first resonator may include a first electrode and a first active layer arranged over the first electrode. The second resonator may include a second active layer arranged over the first active layer, and a second electrode arranged over the second active layer. The stacked first resonator and second resonator may be coupled to a reconfiguration switch for selectively operating at the first operating frequency or the second operating frequency. One of the first resonator and the second resonator is active upon selection by the reconfiguration switch, while the other resonator is inactive.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 17, 2020
    Inventors: Joan Josep GINER DE HARO, Humberto CAMPANELLA PINEDA
  • Patent number: 10833650
    Abstract: A MEMS device including an active layer having a first surface and a second surface is provided. A first electrode and a second electrode, and at least one reconfigurable electrode segment are arranged over the first surface of the active layer. At least one reconfiguration layer is arranged over the second surface of the active layer. The at least one reconfigurable electrode segment and the at least one reconfiguration layer overlaps. One or more via contacts are disposed through the active layer configured to couple the at least one reconfigurable electrode segment and the at least one reconfiguration layer. The at least one reconfiguration layer is coupled to a reconfiguration switch for reconfiguring electrical connections to the at least one reconfigurable electrode segment. The MEMS device is configured to generate different resonant frequencies by reconfiguring the electrical connections to the at least one reconfigurable electrode segment using the reconfiguration switch.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Humberto Campanella Pineda, Joan Josep Giner De Haro, You Qian, Rakesh Kumar
  • Publication number: 20200295165
    Abstract: Transistor-based sensors and fabrication methods for a transistor-based sensor. A semiconductor layer is arranged over a substrate, and an interconnect structure is arranged over the semiconductor layer and the substrate. The semiconductor layer includes first sections composed of a semiconductor material, second sections composed of the semiconductor material, and cavities. The first sections have an alternating arrangement with the second sections in a lateral direction. The semiconductor material of the first sections is polycrystalline, and the semiconductor material of the second sections is single-crystal. First and second openings each extend in a vertical direction through the metallization levels of the interconnect structure to the semiconductor layer or through the substrate to the semiconductor layer. The first opening defines a first fluid inlet coupled to the cavities, and the second opening defines a first fluid outlet coupled to the cavities.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 17, 2020
    Inventors: Vibhor Jain, Joan Josep Giner de Haro, Qizhi Liu, You Qian, Humberto Campanella Pineda
  • Publication number: 20200171541
    Abstract: A MEMS device may include a first electrode region; a first piezoelectric layer arranged over the first electrode region; a second electrode region arranged over the first piezoelectric layer; a second piezoelectric layer arranged over the first piezoelectric layer and the second electrode region; a third electrode region arranged over the second piezoelectric layer; a first input port coupled to the first electrode region and/or the second electrode region for providing a first electrical signal to the first piezoelectric layer to generate a first vibration in the first piezoelectric layer; a second input port coupled to the second electrode region and/or the third electrode region for providing a second electrical signal to the second piezoelectric layer to generate a second vibration in the second piezoelectric layer; and an output port configured to receive an output signal including a superposition of the first vibration and the second vibration.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 4, 2020
    Inventors: Humberto CAMPANELLA PINEDA, Joan Josep GINER DE HARO, You Pak-Chum QIAN, Rakesh KUMAR