Patents by Inventor Joan Preston

Joan Preston has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods for charge dissipation in integrated circuits
    Patent number: 7759173
    Abstract: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: July 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kenneth L. DeVries, Nancy Anne Greco, Joan Preston, Stephen Larry Runyon
  • METHODS AND STRUCTURE FOR CHARGE DISSIPATION IN INTEGRATED CIRCUITS
    Publication number: 20080191309
    Abstract: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.
    Type: Application
    Filed: April 15, 2008
    Publication date: August 14, 2008
    Inventors: Kenneth L. DeVries, Nancy Anne Greco, Joan Preston, Stephen Larry Runyon
  • Method and structure for charge dissipation in integrated circuits
    Patent number: 7408206
    Abstract: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: August 5, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kenneth L. DeVries, Nancy Anne Greco, Joan Preston, Stephen Larry Runyon
  • METHOD AND STRUCTURE FOR CHARGE DISSIPATION IN INTEGRATED CIRCUITS
    Publication number: 20070115606
    Abstract: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.
    Type: Application
    Filed: November 21, 2005
    Publication date: May 24, 2007
    Inventors: Kenneth DeVries, Nancy Greco, Joan Preston, Stephen Runyon