Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.

Abstract: An adhesive material holder further being configured to retain applicators thereof for access by a user. The present invention includes an adhesive retention member that includes a first compartment and a second compartment each being annular in shape having an interior volume. The first compartment and second compartment are formed in the upper surface of the adhesive retention member and have an interior volume configured to retain adhesive or a vessel containing adhesive. A brush retention member is provided wherein the brush retention member includes a body having a first end and a second end. The brush retention member includes a plurality of depressions formed in the upper surface thereof. In an alternative embodiment of the present invention the compartments and depressions are formed on a single body member. The present invention is preferably manufactured from silicone.

Abstract: A storage device having a wide range of operating temperatures is disclosed. Techniques disclosed herein may be used to operate MLC cells at higher temperatures before resorting to thermal throttling. Techniques disclosed herein may be used to operate MLC cells at lower temperatures without needing to pre-heat the storage device. SLC data stored in a first group of memory cells is folded to MLC data stored in a second group of memory cells while an operating temperature is outside a first temperature range. After the operating temperature is within a second temperature range, the data integrity of the MLC data is checked. The SLC data in the first group is folded to MLC data in a third group of memory cells responsive to the MLC data in the second group failing the data integrity check. The foregoing permits the storage device to increase its range in operating temperatures.

Abstract: A storage device having a wide range of operating temperatures is disclosed. Techniques disclosed herein may be used to operate MLC cells at higher temperatures before resorting to thermal throttling. Techniques disclosed herein may be used to operate MLC cells at lower temperatures without needing to pre-heat the storage device. SLC data stored in a first group of memory cells is folded to MLC data stored in a second group of memory cells while an operating temperature is outside a first temperature range. After the operating temperature is within a second temperature range, the data integrity of the MLC data is checked. The SLC data in the first group is folded to MLC data in a third group of memory cells responsive to the MLC data in the second group failing the data integrity check. The foregoing permits the storage device to increase its range in operating temperatures.

Abstract: A storage device having a wide range of operating temperatures is disclosed. Techniques disclosed herein may be used to operate MLC cells at higher temperatures before resorting to thermal throttling. Techniques disclosed herein may be used to operate MLC cells at lower temperatures without needing to pre-heat the storage device. SLC data stored in a first group of memory cells is folded to MLC data stored in a second group of memory cells while an operating temperature is outside a first temperature range. After the operating temperature is within a second temperature range, the data integrity of the MLC data is checked. The SLC data in the first group is folded to MLC data in a third group of memory cells responsive to the MLC data in the second group failing the data integrity check. The foregoing permits the storage device to increase its range in operating temperatures.

Abstract: A storage device having a wide range of operating temperatures is disclosed. Techniques disclosed herein may be used to operate MLC cells at higher temperatures before resorting to thermal throttling. Techniques disclosed herein may be used to operate MLC cells at lower temperatures without needing to pre-heat the storage device. SLC data stored in a first group of memory cells is folded to MLC data stored in a second group of memory cells while an operating temperature is outside a first temperature range. After the operating temperature is within a second temperature range, the data integrity of the MLC data is checked. The SLC data in the first group is folded to MLC data in a third group of memory cells responsive to the MLC data in the second group failing the data integrity check. The foregoing permits the storage device to increase its range in operating temperatures.

Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.

Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.

Abstract: A non-volatile storage system comprises memory cells arranged in groups of memory cells that include programmable select gates and one or more control circuits in communication with the memory cells. The one or more control circuits configured to identify a select gate that needs to be programmed and program the select gate identified to be programmed if a temperature at the non-volatile memory cells is greater than a minimum temperature and defer programming of the select gate identified to be programmed until the temperature at the non-volatile memory cells is greater than the minimum temperature. In some embodiments, the one or more control circuits are configured to perform dummy memory operations on the plurality of non-volatile memory cells to raise the temperature of the non-volatile memory cells in response to determining that the temperature at the non-volatile memory cells is not high enough.

Abstract: A non-volatile storage system comprises memory cells arranged in groups of memory cells that include programmable select gates and one or more control circuits in communication with the memory cells. The one or more control circuits configured to identify a select gate that needs to be programmed and program the select gate identified to be programmed if a temperature at the non-volatile memory cells is greater than a minimum temperature and defer programming of the select gate identified to be programmed until the temperature at the non-volatile memory cells is greater than the minimum temperature. In some embodiments, the one or more control circuits are configured to perform dummy memory operations on the plurality of non-volatile memory cells to raise the temperature of the non-volatile memory cells in response to determining that the temperature at the non-volatile memory cells is not high enough.

Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.

Abstract: Technology is described herein for operating non-volatile storage. In one embodiment, the memory system tracks which adjustments to default values for hard bit read reference voltages are most frequently successful to decode data in non-volatile memory cells. In response to a process that uses only hard bits failing to successfully decode data in a group of the non-volatile memory cells, the memory system attempts to decode the data in the group of non-volatile memory cells using dynamic hard bit read reference voltages and dynamic soft bit read reference voltages that correspond to only a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages. By only using a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages time and power is saved.

Abstract: A non-volatile memory system includes technology for detecting read disturb in open blocks. In one embodiment, the system determines whether a particular block of non-volatile memory cells has been subjected to a minimum number of open block read operations and performs sensing operations for memory cells connected to an open word line of the particular block. The number of errors in the sensed data is determined. If the number of errors is greater than a limit, then the system takes an action to mitigate the read disturb.

Abstract: Technology is described herein for operating non-volatile storage. In one embodiment, the memory system tracks which adjustments to default values for hard bit read reference voltages are most frequently successful to decode data in non-volatile memory cells. In response to a process that uses only hard bits failing to successfully decode data in a group of the non-volatile memory cells, the memory system attempts to decode the data in the group of non-volatile memory cells using dynamic hard bit read reference voltages and dynamic soft bit read reference voltages that correspond to only a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages. By only using a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages time and power is saved.

Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.

Abstract: A non-volatile memory system includes technology for detecting read disturb in open blocks. In one embodiment, the system determines whether a particular block of non-volatile memory cells has been subjected to a minimum number of open block read operations and performs sensing operations for memory cells connected to an open word line of the particular block. The number of errors in the sensed data is determined. If the number of errors is greater than a limit, then the system takes an action to mitigate the read disturb.

Abstract: A storage system and method for generating block allocation groups based on deterministic data patterns are provided. A storage system is provided comprising a memory comprising a plurality of blocks and a controller. The controller is configured to infer characteristics of the memory from data patterns of data stored in the plurality of blocks; and group the plurality of blocks based on the inferred characteristics of the memory.

Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. In one aspect, read voltages are set and optimized based on a time period since a last sensing operation. A timing device such as an n-bit digital counter may be provided for each block of memory cells to track the time. The counter is set to all 1's when the device is powered on. When a sensing operation occurs, the counter is periodically incremented based on a clock. When a next read operation occurs, the value of the counter is cross-referenced to an optimal set of read voltage shifts. Each block of cells may have its own counter, where the counters are incremented using a local or global clock.

Abstract: Performance improvement features can improve the performance of read processes under the right conditions. In order to selectively use the performance improvement features, the system conducts active read sampling to obtain information about bit error rate and then enables the performance improvement feature(s) for future read processes based on the information about bit error rate.