Abstract: An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.

Abstract: An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.

Abstract: A network packet is segmented for transfer through a switch fabric. The last segment of the packet is allowed to exceed the maximum size of previous segments so as to increase the switch fabric utilization. Other features are also provided.

Abstract: An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.

Abstract: An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.

Abstract: A serial channel switch circuit and modular packet switch using the serial channel switch circuits are disclosed. The serial channel switch circuit has a reconfigurable table for internal logical-to-physical channel switch translation. Depending on the slot in which a card containing such a serial channel switch circuit is inserted in the modular packet switch, its serial channel switch circuit may receive a different set of reconfigurable table values that are specific to that location. A global set of logical channel values can be applied to each card, which performs logical-to-physical channel mapping according to its location in the modular packet switch. Other embodiments are also described and claimed.

Abstract: A phase detecting circuit having an adjustable gain curve includes a plurality of phase detectors and a logic circuit. The phase detectors detect phase differences between a data signal and a plurality of clock signals by comparison to output a plurality of control signals. The clock signals have the same frequency but different phases, and the frequency of the data signal is a multiple of the frequency of the clock signals. The logic circuit performs various logic operations according to these control signals to output at least one set of gain control signals for adjusting a gain curve of the phase detecting circuit.

Abstract: An adjustable termination resistor includes a reference resistor, a current mirror circuit, a calibration transistor-resistor array, a digital code generator, a comparator, a decision and latch circuit and a termination resistor. The mirror current generated from the current mirror circuit flows through the calibration transistor-resistor array to result in a comparing voltage across the calibration transistor-resistor array. The resistance of the calibration transistor-resistor array is determined according to a digital code generated from the digital code generator. The voltage level outputted from the comparator is changed from a first state to a second state when the digital code generator up counts to a target digital code such that the comparing voltage is just greater than the reference voltage. The decision and latch circuit records the target digital code into therein. The resistance of the termination resistor is adjustable according to the target digital code.

Abstract: A clock and data recovery circuit having parallel dual path is disclosed, which includes a phase detecting circuit, a first charge pump, a proportional load circuit, a second charge pump, an integration load circuit, and a voltage control oscillating circuit. The phase detecting circuit respectively compares a phase difference between a data signal and a plurality of clock signals to generate two proportional control signal and two integration control signal for respectively controlling the first charge pump and the second charge pump to generate a first current and a second current. The proportional load circuit and the integration load circuit respectively receive the first current and the second current to output a proportional voltage and an integration voltage. The voltage control oscillating circuit adjusts the phase and frequency of the plurality of clock signals in response to the proportional voltage and the integration voltage.

Abstract: A circuit including a Gm-C filter and an automatic Gm-C time constant tuning circuit is provided. The tuning circuit includes a reference conductor, a reference capacitor coupled to the reference conductor, a comparator generating signals according to a reference signal and the voltage signal at the output of the reference conductor, a feedback capacitor, and a charge pump charging and discharging a feedback capacitor according to the output of the comparator. The feedback capacitor provides a control voltage feedback to the tuning circuit and to the Gm-C filter for adjusting the conductance. Hence, in doing so, errors like manufacturing variation and offset can be prevented.

Abstract: An adjustable termination resistor includes a reference resistor, a current mirror circuit, a calibration transistor-resistor array, a digital code generator, a comparator, a decision and latch circuit and a termination resistor. The mirror current generated from the current mirror circuit flows through the calibration transistor-resistor array to result in a comparing voltage across the calibration transistor-resistor array. The resistance of the calibration transistor-resistor array is determined according to a digital code generated from the digital code generator. The voltage level outputted from the comparator is changed from a first state to a second state when the digital code generator up counts to a target digital code such that the comparing voltage is just greater than the reference voltage. The decision and latch circuit records the target digital code into therein. The resistance of the termination resistor is adjustable according to the target digital code.

Abstract: A phase detecting circuit having an adjustable gain curve includes a plurality of phase detectors and a logic circuit The phase detectors detect phase differences between a data signal and a plurality of clock signals by comparison to output a plurality of control signals. The clock signals have the same frequency but different phases, and the frequency of the data signal is a multiple of the frequency of the clock signals. The logic circuit performs various logic operations according to these control signals to output at least one set of gain control signals for adjusting a gain curve of the phase detecting circuit.

Abstract: A clock and data recovery circuit having parallel dual path is disclosed, which includes a phase detecting circuit, a first charge pump, a proportional load circuit, a second charge pump, an integration load circuit, and a voltage control oscillating circuit. The phase detecting circuit respectively compares a phase difference between a data signal and a plurality of clock signals to generate two proportional control signal and two integration control signal for respectively controlling the first charge pump and the second charge pump to generate a first current and a second current. The proportional load circuit and the integration load circuit respectively receive the first current and the second current to output a proportional voltage and an integration voltage. The voltage control oscillating circuit adjusts the phase and frequency of the plurality of clock signals in response to the proportional voltage and the integration voltage.

Abstract: A circuit including a Gm-C filter and an automatic Gm-C time constant tuning circuit is provided. The tuning circuit includes a reference conductor, a reference capacitor coupled to the reference conductor, a comparator generating signals according to a reference signal and the voltage signal at the output of the reference conductor, a feedback capacitor, and a charge pump charging and discharging a feedback capacitor according to the output of the comparator. The feedback capacitor provides a control voltage feedback to the tuning circuit and to the Gm-C filter for adjusting the conductance. Hence, in doing so, errors like manufacturing variation and offset can be prevented.

Abstract: A precise slew rate control line driver includes a slew rate control circuit, a first driver, and a second driver. The slew rate control circuit for slew rate control includes a first operational amplifier and a second operational amplifier. The first driver for driving output signal includes a first current source, a second current source, a first group of switches, and a second group of switches. The second driver for predetermined transient slope includes a capacitor, a third current source, a fourth current source, a third group of switches, and a fourth group of switches.

Abstract: A method for RC time constant tuning includes biasing a reference resistor and charging a reference capacitor, transmitting a start signal to a counter when beginning charging, inputting the results of biasing and charging to a comparator for comparing, and sending a stop signal to the counter when the result of the comparison conforms to a predetermined rule, counting a number of clock cycles received by the counter from the time of receiving the start signal to the time of receiving the stop signal, and deciding a number of resistors or a number of capacitors utilized by an RC filter according to the number of the clock cycles received by the counter.

Abstract: A precise slew rate control line driver includes a slew rate control circuit, a first driver, and a second driver. The slew rate control circuit for slew rate control includes a first operational amplifier and a second operational amplifier. The first driver for driving output signal includes a first current source, a second current source, a first group of switches, and a second group of switches. The second driver for predetermined transient slope includes a capacitor, a third current source, a fourth current source, a third group of switches, and a fourth group of switches.