Abstract: A binary add signal selection type wherein carry signals rather than the usual sum signals are selected from presumed signals by multiplex switching in each bit slice cell of the adder. The new adder is organized into propagation delay time determined stages which include a plurality of sub-stages of multiple bit slice cells each with the carry signals from a previous stage performing the multiplex carry-selection in each stage. The resulting adder is of regular circuit form and adapted to modern fabrication techniques including VLSI and standard cell. arrangements. Mathematical and graphic comparison of the new adder with plural existing adder architectures are included.