Abstract: A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.

Abstract: A tool is provided that determines an optimal number of processor cores or other redundant units in a multiple core processor or system on a chip, along with selecting an associated semiconductor technology and integrated circuit package. The tool integrates design elements, performance and power metrics, manufacturing yields, redundancy, and costs that are both dependent and independent of design features, integrated circuit volume distributions, and boundary conditions, all for a variety of semiconductor technologies and packages. The tool may determine an optimal number of cores for a multiple core processor based on minimizing cost per unit performance or power or redundancy, or other designated design metric, and an associated volume distribution in each technology selected for manufacturing.

Abstract: A method, apparatus, and computer program product for using a multi-core integrated circuit having cores with differing performance characteristics. The cores are arranged into high and low performance groups and tasks are assigned according to their priority to either a high or low performance group.

Abstract: A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.

Abstract: An apparatus and method for providing a multi-core integrated circuit chip that reduces the cost of the package and board while optimizing performance of the cores for use with a single voltage plane. The apparatus and method of the illustrative embodiments make use of a dynamic burn-in technique that optimizes all of the cores on the chip to run at peak performance at a single voltage. Each core is burned-in with a customized burn-in voltage that provides uniform power and performance across the whole chip. This results in a higher burn-in yield and lower overall power in the integrated circuit chip. The optimization of the cores to run at peak performance at a single voltage is achieved through use of the negative bias temperature instability affects on the cores imparted by the burn-in voltages applied.

Abstract: A method of calculating a competitive base wafer cost for use in a model for calculating a packaged integrated circuit (IC) cost. The method includes determining a base wafer price for a first wafer technology at a desired time of analysis and applying a competitive wafer gross margin for the desired time of analysis to the base wafer price to determine the competitive base wafer cost.