Patents by Inventor JoAnne L. Levatin

JoAnne L. Levatin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9586704
    Abstract: A space object modeling system that models the evolution of space debris is provided. The modeling system simulates interaction of space objects at simulation times throughout a simulation period. The modeling system includes a propagator that calculates the position of each object at each simulation time based on orbital parameters. The modeling system also includes a collision detector that, for each pair of objects at each simulation time, performs a collision analysis. When the distance between objects satisfies a conjunction criterion, the modeling system calculates a local minimum distance between the pair of objects based on a curve fitting to identify a time of closest approach at the simulation times and calculating the position of the objects at the identified time. When the local minimum distance satisfies a collision criterion, the modeling system models the debris created by the collision of the pair of objects.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: March 7, 2017
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Sergei Nikolaev, Willem H. De Vries, John R. Henderson, Matthew A. Horsley, Ming Jiang, Joanne L. Levatin, Scot S. Olivier, Alexander J. Pertica, Donald W. Phillion, Harry K. Springer
  • Publication number: 20130124174
    Abstract: An internally parallel PDES (“IP-PDES”) system performs logical processes in parallel and further performs the internal processing of at least one logical process in parallel. Because the IP-PDES system is PDES-based, each logical process may have its processing performed in parallel with the other logical processes. The IP-PDES system allows for certain logical processes to be designated as internally parallel meaning that the logical process, referred to as an IP logical process, has its internal processing also performed in parallel. The IP-DES system allocates multiple nodes for such an IP logical process so that executable code of the IP logical process executes in parallel at the allocated nodes to simulate the occurrence of an event. Internal parallelism within a PDES may help overcome resource limitations and help speed up the overall simulation.
    Type: Application
    Filed: June 4, 2012
    Publication date: May 16, 2013
    Inventors: David R. Jefferson, Alexander Pertica, Matthew C. Brown, Willem H. De Vries, Benjamin J. Fasenfest, Matthew A. Horsley, Ming Jiang, James R. Leek, JoAnne L. Levatin, Segei Nikolaev, Scot S. Olivier, Donald William Phillion, Harry K. Springer