Abstract: A tunable quadrature phase shifter including two branches each constituted by the cascade connection of a filter, an amplifier and a summing circuit, and two cross-connections constituted by amplifiers interconnecting the filter of one branch to the summing circuit of the opposite branch. An accurate 90 degrees phase shift between the two output signals is obtained by controlling the tail currents of the four amplifiers. The phase shifter used in mobile telecommunication transceivers may be easily and accurately tuned because the signals used in the summing circuits all have a similar amplitude. It is further adapted to operate with only a 3 Volt battery supply as used in wireless phones. The bandwidth of the amplifiers is increased by using double differential pair amplifiers which behave as cascode arrangements.

Abstract: The invention concerns an analog to digital converter (ADC1, ADC2) for converting an analog input voltage (Vin) into a digital output voltage (Dout) in at least two stages, (B1, B2, B3, B1', B2', B3'). The reference voltage (Vref) or part thereof driving a stage is applied to that stage via switching means so that the voltage applied to the latter means is determined when the switching means is set, i.e. the latter voltage is not dependent of the setting of the switching means. Two implementations of the converter are described, one (ADC1) which produces the digital signal (Dout) before another analog voltage (Vin) can be processed, and another (ADC2) which allows another analog voltage (Vin) to be processed by a stage after the output of that stage is produced.

Abstract: A synchronizing circuit (SC) is proposed which recovers from input data (ID) applied thereto a data clock signal (DC) synchronous therewith in frequency and in phase. The circuit (SC) consists of a tuned tapped delay line (TDL) generating a plurality of mutually delayed local clock signals (DCS), a latching circuit (SM) sampling these delayed local clock signals at input data level transitions thereby providing sampled versions (LCSV) thereof as well as a comparator (C1) pairwise comparing said delayed local clock signals with respective ones of the sampled versions. It can be verified that with such a circuit the level transitions of the appropriate data clock signal (DC) are generated at the outputs of the comparator (C1) when the latter drives its output high only if a sufficient number of its pairwise comparisons hold.

Abstract: A data, synchronization device adapted to re-synchronize a multi-level digital signal (IN; OUT) with an output or local clock signal (CLKO). In case of a binary signal, the device includes two counter systems (CA1-CC1, MAJ1, SEL1; CA0-CC0, MAJ0, SEL0) each associated with a logical level of the signal and counting the number of successive 1's or 0's respectively. These counter systems produce a count number including the number of counted bits and their level. The device further includes a decoder (DEC) generating in synchronism with the local clock signal (CLKO) a number of bits which is a function of the count numbers. These generated bits constitute the requested output signal (OUT).

Abstract: A differential pair arrangement is disclosed which includes between the poles of a DC supply source the series connection of two parallel first branches and a common second branch. Each first branch includes the series connection of a first impedance Q2, Q3, RL/ Q2', Q3', RL', a main path of a transistor Q1/ Q1'and a second impedance RE/RE', the control electrodes of transistors Q1/ Q1' constituting respective input terminals IN1/ IN2 of the arrangement. The second branch includes a first current source (CCS). The arrangement further includes two third branches between the DC supply source poles, each consisting of the series connection of a second current source ICS/ICS', a respective transistor main path and a resistive impedance means R11, S11, R12, S12/ R11', S11', R12', S12'.

Abstract: Based on the insight that the damping of a tunable filter is both related to its quality factor as to its passband gain, an inventive tuning system is proposed which tunes the quality factor of such a filter to a desired quality factor value by tuning the passband gain of the filter to a desired gain value. Such a tuning system is particularly useful in the field of OTA-C filters and consists of first (P1) and second (P2) tuning paths including such a tunable filter (BIQUAD) and fixed gain amplifiers (B-OTA1, B-OTA2). The gain of the latter amplifiers corresponds to the desired gain values. The tuning system further includes matching means (MM) for equalizing the gains in both tuning paths (P1, P2) by generating a quality factor tuning signal (VTQ) which is applied both to the tunable filter (BIQUAD) and to a replica thereof used as master filter in a data processing path. This matching means (MM) includes current rectifiers (C-REC1, C-REC2) implemented so as to use little hardware.

Abstract: Based on the insight that the voltage-to-current ratio or gain of a capacitor (Z) at a particular reference frequency is the product of its capacitance value with said reference frequency, a tuning system is disclosed which tunes the center frequency of an analog bandpass filter by tuning the characteristic integrator frequency (fc) of an OTA-C integrator by making the transconductance of the operational transconductance amplifier (OTA) thereof equal to the aforementioned gain at that characteristic frequency. Therefore, the tuning system includes a first tuning path in which the OTA, (or a replica thereof) is included and a second tuning path including another amplifier (B-OTA) "degenerated" by the capacitor (Z) so as to produce the required gain. The gains of both these tuning paths are then equalized by matching means (MM) generating a frequency tuning signal (VTF) which is applied to both OTA and OTA-C.

Abstract: The direct conversion receiver DCR receives analog modulating signals with a reference average value and modulated within assigned time slots of a TDMA-structure on a carrier with a carrier frequency FC which changes from time slot to time slot. DCR includes a demodulator circuit DC-coupled to a baseband circuit, the demodulator circuit including a local oscillator LO and a mixer MIX and the baseband circuit including an offset correction circuit OCC/OCC' for updating different variable parameter offset correction values for different FC stored in a memory MEM and compensating offset introduced in DCR. OCC/OCC' determines, upon occurrence of an assigned time slot, an updated offset correction value as a function of an old offset correction value in a corresponding storage location of MEM and the difference between an average value of the analog signal and the reference average value, and thereupon stores the result in the corresponding storage place.

Abstract: Synchronization with an incoming digital signal is timed at a midpoint of the incoming bits by selecting a fine sampling interval that is smaller than the transition period between bits and taking plural adjacent samples, e.g., three samples at the fine sampling interval in a sampling period greater than two bit periods and determining if all the samples were taken from the same bit. If not, either a leftmost or rightmost sample must be unequal to the other samples and the relative timing or phase of the plural samples are shifted right or left in the next sampling period, in a direction opposite from the detected unequal sample, and plural fine samples are again taken, beginning at the newly shifted point.

Abstract: An arrangement includes a differential amplifier pair configured as first and second amplifier branches with first and second input terminals respectively. The first and second amplifier branches are connected at a junction point to a common branch which includes a current source. A control circuit regulates the current of the current source to linearize an input/output characteristic of the amplifier differential pair. The control circuit includes a negative feedback circuit having a comparator, a first input of the comparator being connected to a reference voltage terminal to which an external reference voltage is applied, a second input of the comparator being connected to the amplifier branch junction point and an output of the comparator connected for controlling the current source.

Abstract: The primary device (DSP) is connected to m.times.n secondary devices CESLIC1-4) by one data link (10B) comprising the m.times.n data channels assigned to respective secondary devices (ESLIC1-4) say m clock links (GKC0-1) connected to m respective groups each of n secondary devices (ESLIC1-3; ESLIC2-4) and carrying m clock signals having a same clock frequency and being mutually shifted by 1/m.sup.th of a cycle of the clock frequency, and by n read/write links (RD0-1) connected to n respective groups each of m secondary devices (ESLIC1-2; ESLIC3-4) and carrying n read/write signals mutually shifted by one cycle of the clock frequency, each secondary device (ESLIC1-4) belonging to a distinct pair of one group out of the m groups (ESLIC1-3; ESLIC2-4) and of one group out of the n groups (ESLIC1-2; ESLIC3-4).

Abstract: A multi-sample multi-channel digital decimator filter producing a Finite Impulse filtering Response (FIR) from 128 digital filter coefficients for 4 independent channels with a decimation ratio of 32, i.e. each from 1,024 kHz 1-bit inputs to 32 kHz multibit outputs, splits cyclically the coefficient values in 16 groups of 8, according to the coefficient positions, into 4 Read Only Memory modules (0, 1, 2, 3). The Read Only Memory modules are coupled to the 4 multipliers (MULT 0, 1, 2, 3), wherein the coefficient value is multiplied by that of the input bit, through a multiplexer (MUXI) being able to cycle through 4 distinct conditions. The 4 adder accumulators (ACC 0, 1, 2, 3) are coupled to the outputs of their respective channel multipliers. They each partially compute in parallel outputs words using one sixteenth of the coefficients and the multiplexer rotates these words, thereby enabling complete computation in 4 cycles.

Abstract: A multiplex interpolator handles 4 series of multibit input words . . . , Si, Si+1, . . . applied in parallel at 32 kHz after conversion through an input series to parallel converter (SIPO) and produces 4 series of multibit output words at 256 kHz with the help of a parallel adder/subtractor (ADD) operated in multiplex to compute successively for each of the 4 series of input words, the output words 8Si, 7Si+Si+1, . . . , Si+7Si+1, 8Si+1, . . . , each addition of Si+1-Si being also computed by the adder/subtractor in two steps, first by subtracting (c1) Si from the accumulated (IVC) value and second, by adding (d1) Si+1 to the newly accumulated value, the adder/subtractor being initialized after each pair of steps prior to processing data pertaining to another of the 4 input words in a cyclic manner.

Abstract: Modulator circuit (MOD) with a modulator proper and a correction signal generator. The modulator proper comprises the cascade connection of an amplifier (T11, T21, CS11, T12, T22, CS12) and a first switching circuit (R11, T31, T51, R12, T32, T52), while the generator comprises the cascade connection of the same amplifier and a second switching circuit (R21, T61, T42, R22, T62, T41) having a correction output (P11, P12) coupled to a feedback input (P21, P22) of the amplifier via a feedback circuit (T71, R31, CS21, T72, R32, CS22). The amplifier and the switching circuits are controlled by a modulating signal and a carrier signal respectively and the first and second switching circuits provide a modulated output signal and a correction signal substantially equal to the envelope of the modulated output signal and used to decrease the modulator distortion.

Abstract: An amplifier includes two differential amplifiers which are connected to an output stage comprising two field effect transistors of opposite conductivity typed directly coupled in series between opposite poles of a DC voltage source. The junction between the two output transistors constitutes the output of the amplifier. A negative feedback loop connects the amplifier's output to the inputs of the differential amplifiers. A correction arrangement is provided to prevent excessive current consumption and cross-over distortion. Preferably, the correction arrangement uses a pair of current mirror circuits to generate respective measuring currents proportional to the current in each of the output transistors. Each such measuring current is compared with a reference current.