Abstract: An integrated circuit provides a semiconductor die with I/O bond pads, a power bond pad, and a circuit ground pad. Each I/O bond pad is associated with an input circuit that has an input circuit output lead. Sets of digital logic functional circuitry on the die provide different digital logic functions. Each function includes logic input leads and logic output leads. Output circuits each have an output circuit in lead and an output circuit out lead. Strapping structures, such as vias, formed in the semiconductor die electrically couple input circuits to a selected set of digital logic functions and the selected set of digital logic functions to output circuit in leads. Upper level metal conductors couple output circuit out leads and selected I/O bond pads.

Abstract: An integrated circuit provides a semiconductor die with I/O bond pads, a power bond pad, and a circuit ground pad. Each I/O bond pad is associated with an input circuit that has an input circuit output lead. Sets of digital logic functional circuitry on the die provide different digital logic functions. Each function includes logic input leads and logic output leads. Output circuits each have an output circuit in lead and an output circuit out lead. Strapping structures, such as vias, formed in the semiconductor die electrically couple input circuits to a selected set of digital logic functions and the selected set of digital logic functions to output circuit in leads. Upper level metal conductors couple output circuit out leads and selected I/O bond pads.

Abstract: An integrated circuit provides a semiconductor die with I/O bond pads, a power bond pad, and a circuit ground pad. Each I/O bond pad is associated with an input circuit that has an input circuit output lead. Sets of digital logic functional circuitry on the die provide different digital logic functions. Each function includes logic input leads and logic output leads. Output circuits each have an output circuit in lead and an output circuit out lead. Strapping structures, such as vias, formed in the semiconductor die electrically couple input circuits to a selected set of digital logic functions and the selected set of digital logic functions to output circuit in leads. Upper level metal conductors couple output circuit out leads and selected I/O bond pads.

Abstract: An integrated circuit provides a semiconductor die with I/O bond pads, a power bond pad, and a circuit ground pad. Each I/O bond pad is associated with an input circuit that has an input circuit output lead. Sets of digital logic functional circuitry on the die provide different digital logic functions. Each function includes logic input leads and logic output leads. Output circuits each have an output circuit in lead and an output circuit out lead. Strapping structures, such as vias, formed in the semiconductor die electrically couple input circuits to a selected set of digital logic functions and the selected set of digital logic functions to output circuit in leads. Upper level metal conductors couple output circuit out leads and selected I/O bond pads.

Abstract: One or more high-order bit linear branches of a segmented DAC are implemented as R-2R networks geometrically down-scaled from the DAC binary portion by a selected factor. The resulting increase in closely-located mismatch is compensated for by implementing a trim circuit at a low-order end of each such linear branch. The trim circuit is designed with a number of trim steps to compensate for the selected linear branch down-scaling factor. Each trim step switches a resistance into the low-order end of the linear branch resulting in an even resistance increment or decrement at the lumped linear branch output. The trim circuit is calibrated to provide an amount of trim at the linear branch output such that the lumped resistance of the trimmed linear branch matches the lumped resistance of the binary portion within a selected tolerance (e.g., generally +/?0.5 LSB).

Abstract: A switching regulator (20) including an on-chip power output function (24) and also an interface (26) to which off-chip power output devices (42PU, 42PD) may be connected is disclosed. The switching regulator (20) includes an output enable circuit (25, 125) that senses the presence of external components at one of the terminals (T_PD, TL) of the on-chip power output function (24) or of the interface (26) to determine which of the output functions to enable. In one disclosed embodiment, the output enable circuit (25) detects whether an off-chip power transistor (T_PD) is connected at the interface (26), by charging a passive circuit (R1, C1) and determining whether the charging time constant is affected by the gate capacitance of the external transistor (42PD).

Abstract: A switching regulator (20) including an on-chip power output function (24) and also an interface (26) to which off-chip power output devices (42PU, 42PD) may be connected is disclosed. The switching regulator (20) includes an output enable circuit (25, 125) that senses the presence of external components at one of the terminals (T_PD, TL) of the on-chip power output function (24) or of the interface (26) to determine which of the output functions to enable. In one disclosed embodiment, the output enable circuit (25) detects whether an off-chip power transistor (T_PD) is connected at the interface (26), by charging a passive circuit (R1, C1) and determining whether the charging time constant is affected by the gate capacitance of the external transistor (42PD).

Abstract: A system and method are provided for controlling operation of an actuator for retracting a read/write head of a hard disk drive system. One aspect of the system and method relates to controlling the actuator in response to a retract request command by first decelerating the actuator for a time period and then braking of the actuator for another time period. Another aspect of the system and method relates to controlling operation of the actuator during retract based on a sensed back EMF relative to a target back EMF, which may be selected by a user.

Abstract: A circuit (41) to provide drive voltages to a voice coil motor (VCM) (50) of a hard disk drive (10) has identical high and low side drivers (42, 44, 46, and 48) connected to the VCM (50). Each driver has an output FET (52) selectively connecting the VCM (50) to a control voltage (58). A Class-AB output pair (54 and 54′) in parallel with the output FETs (52 and 52′) provides continuous and linear Class-AB operation at the output node (60) around the crossover point, while the output FETs (52 and 52′) are kept not conducting. This approach offers extremely low level of crossover harmonic distortion. Each FET of the Class-AB pair (54 and 54′) is connected to a biasing FET (56 and 56′) to provide the desired Class-AB quiescent current. Preferably the output FET (52), quiescent current controlling FET (54), and biasing FET (56) are fully integrated.