Patents by Inventor JOAO CLAUDIO AMBROSI

JOAO CLAUDIO AMBROSI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11799888
    Abstract: A network topology analysis and validation system and technique are provided. In some implementations, the system may obtain information in real-time mode or as an off-line data set. The information being representative of a defined network topology type for a computer network and communication connections for devices within the computer network. The computer network analysis may be performed on a subnet of a larger network. A communication topology of the computer network may be compared with the expected (defined) network topology using bipartite and bi-colorization techniques to classify nodes of the computer network. After classification, anomalous communication connections (not in conformance with a standard for the defined network topology) may be identified and colored for presentation to a system administrator. Anomalous communication connections may initiate an alert, event, or alarm, via a system administration monitoring system for real-time notification.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: October 24, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Joao Claudio Ambrosi, Victor Hugo Rebelo Rodrigues, Alex Ferreira Ramires Trajano
  • Patent number: 11200948
    Abstract: Systems are provided for implementing a hybrid resistor-memristor crossbar array, which allows for flexible conductance to be used in implementing the weight matrix of a neural network. The hybrid resistor-memristor crossbar array may include resistor crossbars, each resistor having a static conductance value. The hybrid resistor-memristor crossbar array may also have a memristor coupled to an output line associated with the resistor crossbar array, wherein the memristor has a variable conductance value, and further wherein the static conductance values and the variable conductance value are set to calculate a matrix-vector multiplication associated with a weight matrix of a neural network. An expected range of coefficients for a weight matrix of a neural network can be given by the Discrete Transform Cosine (DCT). Accordingly, the static conductance values of the resistors in the resistors crossbar array are set to values equal to known coefficients of the DCT.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: December 14, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Joao Claudio Ambrosi, Arthur Carvalho Walraven Da Cunha, Jefferson Rodrigo Alves Cavalcante
  • Publication number: 20200389477
    Abstract: A network topology analysis and validation system and technique are provided. In some implementations, the system may obtain information in real-time mode or as an off-line data set. The information being representative of a defined network topology type for a computer network and communication connections for devices within the computer network. The computer network analysis may be performed on a subnet of a larger network. A communication topology of the computer network may be compared with the expected (defined) network topology using bipartite and bi-colorization techniques to classify nodes of the computer network. After classification, anomalous communication connections (not in conformance with a standard for the defined network topology) may be identified and colored for presentation to a system administrator. Anomalous communication connections may initiate an alert, event, or alarm, via a system administration monitoring system for real-time notification.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 10, 2020
    Inventors: Joao Claudio Ambrosi, Victor Hugo Rebelo Rodrigues, Alex Ferreira Ramires Trajano
  • Patent number: 10572269
    Abstract: A non-volatile main memory stores state information of at least one program executing in the system, and metadata indicating whether a system is to be resumed to a prior state on a next start. As part of restarting the system from a mode in which power is removed from the system, the system is resumed to the prior state using the state information stored in the non-volatile main memory, in response to the metadata indicating that the system is to be resumed to the prior state.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: February 25, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Taciano Perez, Carlos Haas Costa, Joao Claudio Ambrosi, Diego Rahn Medaglia, Mauricio Nunes Porto, Roberto Bender
  • Patent number: 10353816
    Abstract: A system includes a non-volatile memory to store a page cache that contains pages of data allocated by an operating system, the pages in the page cache being persistent across a power cycle of the system. The page cache is located in a specified region of the non-volatile memory and is to store the pages of data without tagging a memory region.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: July 16, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Christian Perone, Diego Rahn Medaglia, Joao Claudio Ambrosi, James M Mann, Craig Walrath
  • Patent number: 10331457
    Abstract: In one example, a computer having a processor and a byte-addressable non-volatile read-write main memory. The memory is partitioned into plural regions, each region having at least one defined operational property. At least one of the regions is a metadata region to store plural data sets. Each data set specifies a location in memory, and the at least one operational property, of a corresponding one of the regions.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: June 25, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Carlos Haas Costa, Taciano Dreckmann Perez, Diego Rahn Medaglia, Mauricio Nunes Porto, Roberto Bender, Joao Claudio Ambrosi
  • Patent number: 10206092
    Abstract: Some examples provide a system to automatically discover network devices. The system enables a network device discovery protocol with a transmit mode and a receive mode on a network device. The system enables an auxiliary communication protocol on the network device. The system broadcasts the network device discovery protocol records from the network device including local neighbors and connectivity information. The system engine processes topological information using the auxiliary communication protocol and timing cycles to update age of a set of topology information records.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 12, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Peter Erik Mellquist, Joao Claudio Ambrosi, Bryan Stiekes, Raul Ney da Silva Lima, Victor Hugo Rebelo Rodrigues, Alex Ferreira Ramires Trajano
  • Publication number: 20180196748
    Abstract: A system includes a non-volatile memory to store a page cache that contains pages of data allocated by an operating system, the pages in the page cache being persistent across a power cycle of the system. The page cache is located in a specified region of the non-volatile memory and is to store the pages of data without tagging a memory region.
    Type: Application
    Filed: January 28, 2015
    Publication date: July 12, 2018
    Inventors: JOAO CLAUDIO AMBROSI, JAMES M MANN, CRAIG WALRATH, Christian PERONE, Diego Rahn MEDAGLIA
  • Publication number: 20170046176
    Abstract: A non-volatile main memory stores state information of at least one program executing in the system, and metadata indicating whether a system is to be resumed to a prior state on a next start. As part of restarting the system from a mode in which power is removed from the system, the system is resumed to the prior state using the state information stored in the non-volatile main memory, in response to the metadata indicating that the system is to be resumed to the prior state.
    Type: Application
    Filed: April 29, 2014
    Publication date: February 16, 2017
    Inventors: Taciano Perez, Carlos Haas Costa, Joao Claudio Ambrosi, Diego Rahn Medaglia, Mauricio Nunes Porto, Roberto Bender
  • Publication number: 20160321083
    Abstract: In one example, a computer having a processor and a byte-addressable non-volatile read-write main memory. The memory is partitioned into plural regions, each region having at least one defined operational property. At least one of the regions is a metadata region to store plural data sets. Each data set specifies a location in memory, and the at least one operational property, of a corresponding one of the regions.
    Type: Application
    Filed: January 22, 2014
    Publication date: November 3, 2016
    Inventors: CARLOS HAAS COSTA, TACIANO DRECKMANN PEREZ, DIEGO RAHN MEDAGLIA, MAURICIO NUNES PORTO, ROBERTO BENDER, JOAO CLAUDIO AMBROSI