Patents by Inventor Joao Manuel Paiva Cardoso

Joao Manuel Paiva Cardoso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for optimizing code for field programmable gate arrays
    Patent number: 11656857
    Abstract: A method for the generation of a hardware accelerator (20) is described. The method comprises inputting (110) a program (105) with a plurality of lines of code describing an algorithm to be implemented on the hardware accelerator (20) and generating (125) a dataflow graph in memory from the inputted program (105). The dataflow graph is optimized and an output program (140) created from the dataflow graph is output. The output program (140) is then provided to a high-level synthesis tool for generating the hardware accelerator (20).
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 23, 2023
    Assignee: INESC TEC—Instituto de Engenharia de Sistemas
    Inventors: Afonso Soares Canas Ferreira, João Manuel Paiva Cardoso
  • METHOD AND APPARATUS FOR OPTIMIZING CODE FOR FIELD PROGRAMMABLE GATE ARRAYS
    Publication number: 20210382702
    Abstract: A method for the generation of a hardware accelerator (20) is described. The method comprises inputting (110) a program (105) with a plurality of lines of code describing an algorithm to be implemented on the hardware accelerator (20) and generating (125) a dataflow graph in memory from the inputted program (105). The dataflow graph is optimized and an output program (140) created from the dataflow graph is output. The output program (140) is then provided to a high-level synthesis tool for generating the hardware accelerator (20).
    Type: Application
    Filed: August 9, 2019
    Publication date: December 9, 2021
    Inventors: AFONSO SOARES CANAS FERREIRA, JOÃO MANUEL PAIVA CARDOSO
  • Method for processing data
    Patent number: 10031733
    Abstract: A method for operating a system on a chip comprising a conventional processor unit (CISC, RISC, VLIW, DSP) and an array processor having a multidimensional arrangement of arithmetic units. Operation information for the array processor are stored in a memory shared between the conventional processor and the array processor. At runtime the conventional processor points the array processor to the memory area comprising the operation information. A management unit inside the array processor is autonomously loading the operation information into the array processor.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: July 24, 2018
    Assignee: Scientia Sol Mentis AG
    Inventors: Martin Vorbach, Frank May, Markus Weinhardt, Joao Manuel Paiva Cardoso
  • METHOD FOR PROCESSING DATA
    Publication number: 20140297948
    Abstract: A method for operating a system on a chip comprising a conventional processor unit (CISC, RISC, VLIW, DSP) and an array processor having a multidimensional arrangement of arithmetic units. Operation information for the array processor are stored in a memory shared between the conventional processor and the array processor. At runtime the conventional processor points the array processor to the memory area comprising the operation information.
    Type: Application
    Filed: March 24, 2014
    Publication date: October 2, 2014
    Applicant: PACT XPP TECHNOLOGIES AG
    Inventors: Martin VORBACH, Frank May, Markus Weinhardt, Joao Manuel Paiva Cardoso
  • METHOD FOR PROCESSING DATA
    Publication number: 20100095094
    Abstract: A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.
    Type: Application
    Filed: December 17, 2009
    Publication date: April 15, 2010
    Inventors: Martin VORBACH, Armin Nückel, Frank May, Markus Weinhardt, Joao Manuel Paiva Cardoso
  • Method for processing data
    Patent number: 7657877
    Abstract: A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: February 2, 2010
    Assignee: Pact XPP Technologies AG
    Inventors: Martin Vorbach, Armin Nückel, Frank May, Markus Weinhardt, Joao Manuel Paiva Cardoso
  • Data processing method
    Publication number: 20040243984
    Abstract: A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.
    Type: Application
    Filed: June 18, 2004
    Publication date: December 2, 2004
    Inventors: Martin Vorbach, Armin Nuckel, Frank May, Markus Weinhardt, Joao Manuel Paiva Cardoso