Abstract: An integrated circuit coupled to an external serial bus is presented. A method for prefetching data from an external serial bus is presented. The integrated circuit comprises a serial interface, a data cache, and a prefetch control unit. The serial interface detects a data address on the serial bus and reads data elements from data storage units. The data storage units may be internal or external to the integrated circuit. The data cache is coupled to the serial interface via an internal bus. The prefetch control unit instructs the serial interface to prefetch a data element associated with the data address by reading the data element from a target data storage unit associated with the data address. The data element and the data address are written to the data cache. When a read request is detected, the data element can be quickly accessed from the data cache.

Abstract: A distributed power management system comprising at least two power management integrated circuits PMICs is presented. A master power management integrated circuit PMIC supplies power to a subsystem of an electronic device based on a current state of a master finite state machine FSM executed by the master PMIC. A slave power management integrated circuit PMIC executes a slave finite state machine FSM and supplies power to another subsystem based on the current state of the master FSM. For synchronizing the operation of both PMIC, the master PMIC transmits, to the slave PMIC, synchronization information indicative of at least one of an input signal of the master FSM, a state of the master FSM, a state transition of the master FSM, and an output signal generated by the master FSM. A distributed power management method is presented which is carried out by a master PMIC and a slave PMIC.

Abstract: An integrated circuit coupled to an external serial bus is presented. A method for prefetching data from an external serial bus is presented. The integrated circuit comprises a serial interface, a data cache, and a prefetch control unit. The serial interface detects a data address on the serial bus and reads data elements from data storage units. The data storage units may be internal or external to the integrated circuit. The data cache is coupled to the serial interface via an internal bus. The prefetch control unit instructs the serial interface to prefetch a data element associated with the data address by reading the data element from a target data storage unit associated with the data address. The data element and the data address are written to the data cache. When a read request is detected, the data element can be quickly accessed from the data cache.

Abstract: A distributed power management system comprising at least two power management integrated circuits PMICs is presented. A master power management integrated circuit PMIC supplies power to a subsystem of an electronic device based on a current state of a master finite state machine FSM executed by the master PMIC. A slave power management integrated circuit PMIC executes a slave finite state machine FSM and supplies power to another subsystem based on the current state of the master FSM. For synchronizing the operation of both PMIC, the master PMIC transmits, to the slave PMIC, synchronization information indicative of at least one of an input signal of the master FSM, a state of the master FSM, a state transition of the master FSM, and an output signal generated by the master FSM. A distributed power management method is presented which is carried out by a master PMIC and a slave PMIC.

Abstract: A method for charging a battery is provided, wherein current pulses are supplied to the battery, wherein each pulse is followed by a rest period during which no current is supplied to the battery, and wherein the state of charge of the battery is determined during the rest period.

Abstract: A method for charging a battery is provided, wherein current pulses are supplied to the battery, wherein each pulse is followed by a rest period during which no current is supplied to the battery, and wherein the state of charge of the battery is determined during the rest period.