Abstract: Accordingly, embodiments of the present invention provide a method and apparatus for low-latency, low-power dissipation analog-to-digital conversion. A SAR ADC is implemented using internal signal attenuation, after the signal being sampled, to convert accuracy into speed, allowing higher clock frequency and therefore smaller latency. Some embodiments of the low-latency, low-power dissipation analog-to-digital converters described herein are particularly well-suited to industrial motor control applications, such as analog-to-digital converters that convert relatively high amplitude signals to control motors of robotic or automated industrial manufacturing systems and devices. The reduced latency data conversion of the ADCs allows motor control systems to quickly respond to unanticipated stimulus, which is critical for certain applications, such as robots operating in noisy and unpredictable environments.

Abstract: In an embodiment, a digital-to-analog converter (DAC) includes inputs for receiving first and second signals encoded as a digital signal pair including overlapping low value portions that are substantially equal in duration to overlapping high value portions, within a frame. The DAC further includes an output terminal for providing an analog signal and includes first and second switches responsive to the first and second signals alter a level of the analog signal based on values of the first and second signals to provide a mismatch-immune DAC functionality. In one instance, the switches couple current sources to a common node. In another instance, the switches configure a resistive network to alter a resistance at an input to an amplifier.

Abstract: In an embodiment, a digital-to-analog converter (DAC) includes inputs for receiving first and second signals encoded as a digital signal pair including overlapping low value portions that are substantially equal in duration to overlapping high value portions, within a frame. The DAC further includes an output terminal for providing an analog signal and includes first and second switches responsive to the first and second signals alter a level of the analog signal based on values of the first and second signals to provide a mismatch-immune DAC functionality. In one instance, the switches couple current sources to a common node. In another instance, the switches configure a resistive network to alter a resistance at an input to an amplifier.