Abstract: A method of design and an implementation system for reduced-state Viterbi detectors for intersymbol interference channels are provided. The method uses a complement states grouping technique that comprises the steps of finding the state distances between complement states; forming the reduced-state trellis by grouping the complement states with state distance no less than the minimum free distance; and by keeping the complement states with state distance less than minimum free distance unchanged. The resultant reduced-state Viterbi detector has negligible performance loss compared to the full-state Viterbi detector while the complexity is reduced by a factor of about two.

Abstract: A method of design and an implementation system for reduced-state Viterbi detectors for intersymbol interference channels are provided. The method uses a complement states grouping technique that comprises the steps of finding the state distances between complement states; forming the reduced-state trellis by grouping the complement states with state distance no less than the minimum free distance; and by keeping the complement states with state distance less than minimum free distance unchanged. The resultant reduced-state Viterbi detector has negligible performance loss compared to the full-state Viterbi detector while the complexity is reduced by a factor of about two.

Abstract: A method of design and an implementation system for reduced-state Viterbi detectors for intersymbol interference channels is provided. The method uses a complement states grouping technique that comprises the steps of finding the state distances between complement states; forming the reduced-state trellis by grouping the complement states with state distance no less than the minimum free distance; and by keeping the complement states with-state distance less than minimum free distance unchanged. The resultant reduced-state Viterbi detector has negligible performance loss compared to the full-state Viterbi detector while the complexity is reduced by a factor of about two.

Abstract: A method of design and an implementation system for reduced-state Viterbi detectors for intersymbol interference channels are provided. The method uses a complement states grouping technique that comprises the steps of finding the state distances between complement states; forming the reduced-state trellis by grouping the complement states with state distance no less than the minimum free distance; and by keeping the complement states with state distance less than minimum free distance unchanged. The resultant reduced-state Viterbi detector has negligible performance loss compared to the full-state Viterbi detector while the complexity is reduced by a factor of about two.

Abstract: A method of design and implementation of trellis codes for intersymbol interference channels is provided wherein a set of input vectors is mapped to a set of output vectors comprising the steps of forming a minimized basis having a set of minimized basis vectors configured for a set of channel output signals corresponding to the set of output vectors; selecting the smallest member of the set of minimized basis vectors as a coset vector; forming a partition basis by adding the coset vector to at least one member of the set of the minimized basis vectors; and forming a subsequent minimized basis from the partition basis. These codes circumvent the necessity for intersymbol interference removal, thereby reducing equalization complexity.

Abstract: A digital magnetic recording system comprises an input for a binary-encoded data signal comprising two symbols. The binary signal is converted, using a binary-to-ternary convolutional encoder, to a ternary signal comprising three symbols. The ternary signal is recorded onto a magnetic medium wherein two symbols are recorded using conventional saturation recording and a third symbol is recorded using a nonoriented state. The nonoriented state results from the application to the medium of a high-frequency oscillating magnetic flux. The recorded signal is subsequently reproduced and equalized. A Viterbi algorithm is used to convert the equalized signal back to the original binary signal which is then output from the system.