Patents by Inventor Joaquim Lopez Mestre

Joaquim Lopez Mestre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240125839
    Abstract: An emulator system for testing an electrical product in a closed circuit, including a first power electronic structure to emulate a voltage source, connectable to the input of the electrical product; a second power electronic structure to emulate an electronic load, connectable to the output of the electrical product; a direct current bus connected between the first and second structure; a power supply configured to be connected to a general electrical grid and power the bus; and a control module in communication with all elements of the system. Once the electrical product is connected between the emulated source and load, a closed circuit is established in which the emulated source consumes power from the bus to test the product and the emulated electronic load reinjects the power consumed into the bus.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 18, 2024
    Inventors: Joaquim Lopez Mestre, Marta Berge Garcia
  • Patent number: 9360506
    Abstract: The present invention relates to a system for monitoring the electric network voltage waveform, comprising: switching means (11) connected to the voltage lines (A, B, C) of a three-phase system, comprising two thyristors (T1, T2) connected to two of the voltage lines (A, B, C) and at least two capacitors (C1, C2) connected to said thyristors (T1, T2), said means (11) being configured to open and close said thyristors (T1, T2) in response to a trigger signal; means for measuring (12) the voltages in said voltage lines and at the input of said capacitors; a thyristor trigger circuit (14) for providing a trigger signal to either thyristor (DT1, DT2) when the voltage in the terminals of said thyristor (T1, T2) crosses zero; control means (13, 23) for giving said trigger order (OD) or not.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: June 7, 2016
    Assignee: ARTECHE LANTEGI ELKARTEA, S.A.
    Inventors: Joan Gabriel Bergas, Joaquim López Mestre, Hector Ali Rivas Guerrero, Natalia Sangroniz Palacio, César Chávez Soria
  • Publication number: 20140062458
    Abstract: The present invention relates to a system for monitoring the electric network voltage waveform, comprising: switching means (11) connected to the voltage lines (A, B, C) of a three-phase system, comprising two thyristors (T1, T2) connected to two of the voltage lines (A, B, C) and at least two capacitors (C1, C2) connected to said thyristors (T1, T2), said means (11) being configured to open and close said thyristors (T1, T2) in response to a trigger signal; means for measuring (12) the voltages in said voltage lines and at the input of said capacitors; a thyristor trigger circuit (14) for providing a trigger signal to either thyristor (DT1, DT2) when the voltage in the terminals of said thyristor (T1, T2) crosses zero; control means (13, 23) for giving said trigger order (OD) or not.
    Type: Application
    Filed: February 18, 2011
    Publication date: March 6, 2014
    Applicant: ARTECHE LANTEGI ELKARTEA, S.A.
    Inventors: Joan Gabriel Bergas, Joaquim López Mestre, Hector Ali Rivas Guerrero, Natalia Sangroniz Palacio, César Chávez Soria