Patents by Inventor Joaquin Hinojosa
Joaquin Hinojosa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7822942Abstract: An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.Type: GrantFiled: March 25, 2008Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Michael J. Corrigan, Paul LuVerne Godtland, Joaquin Hinojosa, Cathy May, Naresh Nayar, Edward John Silha
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Patent number: 7752354Abstract: A management system that controls a restart interface in a data processing system. The management system switches control of the interface from a distributed network managed by the caches to the management system. The management system is capable of detecting errors and seizing control of the interface in order to remedy any errors that occur within the interface.Type: GrantFiled: February 11, 2005Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Miles Robert Dooley, Joaquin Hinojosa, Bruce Joseph Ronchetti, Anthony Saporito
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Patent number: 7660965Abstract: A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.Type: GrantFiled: January 7, 2008Date of Patent: February 9, 2010Assignee: International Business Machines CorporationInventors: Joaquin Hinojosa, Sheldon B. Levenstein, Bruce Joseph Ronchetti
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Publication number: 20080168254Abstract: An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.Type: ApplicationFiled: March 25, 2008Publication date: July 10, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael J. Corrigan, Paul LuVerne Godtland, Joaquin Hinojosa, Cathy May, Naresh Nayar, Edward John Silha
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Patent number: 7389400Abstract: An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.Type: GrantFiled: December 15, 2005Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: Michael J. Corrigan, Paul LuVerne Godtland, Joaquin Hinojosa, Cathy May, Naresh Nayar, Edward John Silha
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Publication number: 20080104599Abstract: A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.Type: ApplicationFiled: January 7, 2008Publication date: May 1, 2008Inventors: Joaquin Hinojosa, Sheldon Levenstein, Bruce Ronchetti
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Patent number: 7350051Abstract: A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.Type: GrantFiled: February 9, 2005Date of Patent: March 25, 2008Assignee: International Business Machines CorporationInventors: Joaquin Hinojosa, Sheldon B. Levenstein, Bruce Joseph Ronchetti
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Publication number: 20070143565Abstract: An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.Type: ApplicationFiled: December 15, 2005Publication date: June 21, 2007Applicant: International Business Machines CorporationInventors: Michael Corrigan, Paul Godtland, Joaquin Hinojosa, Cathy May, Naresh Nayar, Edward Silha
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Patent number: 7116569Abstract: A CAM system is disclosed in which requests for address translation are provided as input search data to a dynamic compare bitline generator. The dynamic compare bitline generator also receives a compare mask and applies the compare mask to associated input search data bits on a per bit basis. The mask contains information that specifies a selected page size and a selected logic mode that can be applied to a compare array in which the specified search is conducted. The compare array is coupled to a data array to which the compare array indicates a result of the search.Type: GrantFiled: February 11, 2005Date of Patent: October 3, 2006Assignee: International Business Machines CorporationInventors: Joaquin Hinojosa, Eric Jason Fluhr, Michael Ju Hyeok Lee, Jose Angel Paredes, Ed Seewann
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Publication number: 20060181909Abstract: A CAM system is disclosed in which requests for address translation are provided as input search data to a dynamic compare bitline generator. The dynamic compare bitline generator also receives a compare mask and applies the compare mask to associated input search data bits on a per bit basis. The mask contains information that specifies a selected page size and a selected logic mode that can be applied to a compare array in which the specified search is conducted. The compare array is coupled to a data array to which the compare array indicates a result of the search.Type: ApplicationFiled: February 11, 2005Publication date: August 17, 2006Applicant: International Business Machines CorporationInventors: Joaquin Hinojosa, Eric Fluhr, Michael Lee, Jose Paredes, Ed Seewann
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Publication number: 20060184822Abstract: A management system that controls a restart interface in a data processing system. The management system switches control of the interface from a distributed network managed by the caches to the management system. The management system is capable of detecting errors and seizing control of the interface in order to remedy any errors that occur within the interface.Type: ApplicationFiled: February 11, 2005Publication date: August 17, 2006Applicant: International Business Machines CorporationInventors: Miles Dooley, Joaquin Hinojosa, Bruce Ronchetti, Anthony Saporito
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Publication number: 20060179264Abstract: A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.Type: ApplicationFiled: February 9, 2005Publication date: August 10, 2006Applicant: International Business Machines CorporationInventors: Joaquin Hinojosa, Sheldon Levenstein, Bruce Ronchetti
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Patent number: 6981128Abstract: In a system with multiple execution units, instructions are queued to allow efficient dispatching. One load/store unit (LSU) may have a store instruction pending to a real address and a second LSU may have a load instruction pending to the same real address. An SMT system has an atomic store quad word (SQW) instruction with a data path that is only double wide and the SQW requires two cycles to complete. The SMT system requires a method to prevent between collisions in a store reorder queue (SRQ) STQ. The real address of a load word (LW) one thread is compared to the real addresses in the SRQ of the second thread. If the SQW with a real address matching the real address of the LW has not committed both of its double words, then the LW of the second thread is rejected.Type: GrantFiled: April 24, 2003Date of Patent: December 27, 2005Assignee: International Business Machines CorporationInventors: Eric J. Fluhr, Joaquin Hinojosa, Ronald N. Kalla, Bruce J. Ronchetti, Balaram Sinharoy
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Publication number: 20040216104Abstract: In a system with multiple execution units, instructions are queued to allow efficient dispatching. One load/store unit (LSU) may have a store instruction pending to a real address and a second LSU may have a load instruction pending to the same real address. An SMT system has an atomic store quad word (SQW) instruction with a data path that is only double wide and the SQW requires two cycles to complete. The SMT system requires a method to prevent between collisions in a store reorder queue (SRQ) STQ. The real address of a load word (LW) one thread is compared to the real addresses in the SRQ of the second thread. If the SQW with a real address matching the real address of the LW has not committed both of its double words, then the LW of the second thread is rejected.Type: ApplicationFiled: April 24, 2003Publication date: October 28, 2004Applicant: International Business Machines CorporationInventors: Eric J. Fluhr, Joaquin Hinojosa, Ronald N. Kalla, Bruce J. Ronchetti, Balaram Sinharoy
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Patent number: 5502732Abstract: A system and method for checking the test logic contained in a computer memory system during POST such that any errors can be determined and made available to the system software prior to beginning processing operations. Single and double bit errors are induced which the ECC logic must identify and correct. The CPU compares the data that is written to memory with the data that is read back. Thus, since it is known that an error occurred, due to the induced error provided by the present invention, identical data will verify that the ECC correction logic is working properly. More specifically, a multiplexer is provided in the data write path which substitutes a constant set of identical bits for the actual data generated by the CPU. ECC bits are generated based on the actual generated test data, rather than the inserted identical bits. The substituted data bits and generated ECC bits are then stored in memory. An error condition is identified when the data and ECC code is read back from memory.Type: GrantFiled: September 20, 1993Date of Patent: March 26, 1996Assignee: International Business Machines CorporationInventors: Ronald X. Arroyo, William E. Burky, Tricia A. Gruwell, Joaquin Hinojosa
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Patent number: 5446845Abstract: Data bus steering logic routes data between various byte lanes of the system bus. Additionally, control signals are provided which allow the connected device and the steering logic to communicate and respond to requests made by the CPU. The steering logic provides a path between the attached device and the byte lanes of the system bus, to which the device is not directly connected. During load and store operations data is transferred via the steering logic and directly between the device and CPU on to the portion of the system bus that it is directly connected to. The steering logic includes a multiplexer, latch, buffer, driver and the like for each lane of data on the system bus. For example, if the system bus is 64 bits wide and a 32 bit device is connected to one-half of the bus, the steering logic will provide a path from the 32 bit device to the other 32 bits of the system bus not directly connected to the device.Type: GrantFiled: September 20, 1993Date of Patent: August 29, 1995Assignee: International Business Machines CorporationInventors: Ronald X. Arroyo, William E. Burky, Tricia A. Gruwell, Joaquin Hinojosa