Abstract: An electronic device comprises at least one voltage regulating circuit portion connected to a first node and a current source connected to a second node. A detection circuit portion is arranged to determine whether an inductor is connected between the first and second nodes and to produce a ready signal indicative thereof. The voltage regulating circuit portion requires the inductor to be connected between the first and second nodes in order to operate.

Abstract: An electronic data processing device comprises: a processor (1); a serial interface comprising a connection for incoming data (16) and a connection for outgoing data (18); a hardware serial-interface controller (6) for controlling the serial interface; and a reception buffer (22) for receiving incoming data. The processor is arranged automatically to read data written to the reception buffer. The device is arranged so that the processor can indicate to the serial interface controller that it is unable to accept data. The controller is arranged to respond to incoming data by sending a rejection message from the outgoing serial connection and to prevent incoming data from being placed in the reception buffer.

Abstract: A microcontroller (1) comprises a processor (2), a memory (3), a bus (15) connecting the processor (2) and the memory (3) and a memory watch unit (14), comprising one or more memory-watch event registers and one or more configuration registers. The memory watch unit (14) is arranged to monitor memory access instructions on the bus (15), and can be configured, using the one or more configuration registers, to (i) detect a memory access instruction for a memory address in a configurable watch region of the memory (3), and (ii) change the contents of one or more memory-watch event registers in response to such a detection.

Abstract: A microcontroller (2) has a processor (6), peripherals (18, 20, 22, 24, 26), a programmable peripheral interconnect (PPI) (10), an event-generating unit (EGU) (17), and a memory (8). The peripherals respond to task signals from the PPI. The EGU responds to a predetermined change to the contents of an event-generating register (57, 59) by signalling an event to the PPI. Stored PPI mappings can map an EGU event to a task of one of the peripherals. Mappings from one EGU event to two or more peripheral tasks cause the PPI to respond to an event signal from the EGU by sending the respective task signals within a maximum time limit. Software in the memory comprises instructions to store such mappings in a mapping memory, and to make the predetermined change to the contents of the event-generating register. In another aspect, an interrupt-generating unit (17) is arranged to send an interrupt to the processor (6) in response to receiving a task signal from the PPI (10).

Abstract: A microcontroller (1) comprises a processor (2), a memory (3), a bus (15) connecting the processor (2) and the memory (3) and a memory watch unit (14), comprising one or more memory-watch event registers and one or more configuration registers. The memory watch unit (14) is arranged to monitor memory access instructions on the bus (15), and can be configured, using the one or more configuration registers, to (i) detect a memory access instruction for a memory address in a configurable watch region of the memory (3), and (ii) change the contents of one or more memory-watch event registers in response to such a detection.

Abstract: An integrated circuit device comprises: a first power domain (100) including a processor (2) and non-volatile memory (10) connected to the processor; and a second power domain (200) including an access port (12) connected to the non-volatile memory. The access port is further connected to an electrical interface (4) suitable for connection to a debugger.

Abstract: A microcontroller (2) has a processor (6), peripherals (18, 20, 22, 24, 26), a programmable peripheral interconnect (PPI) (10), an event-generating unit (EGU) (17), and a memory (8). The peripherals respond to task signals from the PPI. The EGU responds to a predetermined change to the contents of an event-generating register (57, 59) by signalling an event to the PPI. Stored PPI mappings can map an EGU event to a task of one of the peripherals. Mappings from one EGU event to two or more peripheral tasks cause the PPI to respond to an event signal from the EGU by sending the respective task signals within a maximum time limit. Software in the memory comprises instructions to store such mappings in a mapping memory, and to make the predetermined change to the contents of the event-generating register. In another aspect, an interrupt-generating unit (17) is arranged to send an interrupt to the processor (6) in response to receiving a task signal from the PPI (10).

Abstract: An integrated circuit microprocessor device comprises a central processing unit (CPU) and a general purpose input or output module (2) having a plurality of external connections (4). The external connections are configured by the general purpose input or output module to provide respective inputs to the device. The device further comprises respective memory locations (6) corresponding to each of the external connections. The memory locations are arranged to record a change of state on one or more of the external connections in the event that the change of state occurs while the central processing unit is in a low power state or otherwise unable to react to the change of state.

Abstract: An electronic data processing device comprises: a processor (1); a serial interface comprising a connection for incoming data (16) and a connection for outgoing data (18); a hardware serial-interface controller (6) for controlling the serial interface; and a reception buffer (22) for receiving incoming data. The processor is arranged automatically to read data written to the reception buffer. The device is arranged so that the processor can indicate to the serial interface controller that it is unable to accept data. The controller is arranged to respond to incoming data by sending a rejection message from the outgoing serial connection and to prevent incoming data from being placed in the reception buffer.

Abstract: Peripherals (18, 20, 22, 24, 26) are connected to a processor (6) and a programmable peripheral interconnect (10) is connected to each peripheral. One of the peripherals (18) is configured to signal an event to the interconnect, and one of the peripherals (20) is configured to respond to a task signal from the interconnect by performing a task. The task-receiving peripheral (20) has a task register (40), addressable by the processor (6), and performs the task in response to a change in the contents of the register (40). The interconnect (10) accesses a memory (14) in which a mapping is stored between an event of a first peripheral (18) and a task of a second peripheral (20), the mapping comprising (i) an identification of the event, and (ii) the address of a task register (40). The mapping causes the interconnect (10) to provide a channel by sending a task signal to the second peripheral (20) in response to a signal of the event from the first peripheral (18).

Abstract: Peripherals (18, 20, 22, 24, 26) are connected to a processor (6) and a programmable peripheral interconnect (10) is connected to each peripheral. One of the peripherals (18) is configured to signal an event to the interconnect, and one of the peripherals (20) is configured to respond to a task signal from the interconnect by performing a task. The task-receiving peripheral (20) has a task register (40), addressable by the processor (6), and performs the task in response to a change in the contents of the register (40). The interconnect (10) accesses a memory (14) in which a mapping is stored between an event of a first peripheral (18) and a task of a second peripheral (20), the mapping comprising (i) an identification of the event, and (ii) the address of a task register (40). The mapping causes the interconnect (10) to provide a channel by sending a task signal to the second peripheral (20) in response to a signal of the event from the first peripheral (18).

Abstract: A device for analyzing the behaviour of a microcontroller comprising a microcontroller integrated circuit (2), at least one instrument selected from the group comprising analyzers (12) and generators (14), and an interconnection module (8) comprising configurable interconnections between said microcontroller integrated circuit (2) and said instrument (12, 14). The device also comprises software (16) arranged to control said interconnection module (8) in order to determine said interconnections based on a function selected by a user and determined capabilities and connections of the microcontroller integrated circuit (2), wherein the device is itself configured to determine at least some capabilities and connections of the microcontroller integrated circuit (2).

Abstract: Peripherals (18, 20, 22, 24, 26) are connected to a processor (6) and a programmable peripheral interconnect (10) is connected to each peripheral. One of the peripherals (18) is configured to signal an event to the interconnect, and one of the peripherals (20) is configured to respond to a task signal from the interconnect by performing a task. The task-receiving peripheral (20) has a task register (40), addressable by the processor (6), and performs the task in response to a change in the contents of the register (40). The interconnect (10) accesses a memory (14) in which a mapping is stored between an event of a first peripheral (18) and a task of a second peripheral (20), the mapping comprising (i) an identification of the event, and (ii) the address of a task register (40). The mapping causes the interconnect (10) to provide a channel by sending a task signal to the second peripheral (20) in response to a signal of the event from the first peripheral (18).

Abstract: Peripherals (18, 20, 22, 24, 26) are connected to a processor (6) and a programmable peripheral interconnect (10) is connected to each peripheral. One of the peripherals (18) is configured to signal an event to the interconnect, and one of the peripherals (20) is configured to respond to a task signal from the interconnect by performing a task. The task-receiving peripheral (20) has a task register (40), addressable by the processor (6), and performs the task in response to a change in the contents of the register (40). The interconnect (10) accesses a memory (14) in which a mapping is stored between an event of a first peripheral (18) and a task of a second peripheral (20), the mapping comprising (i) an identification of the event, and (ii) the address of a task register (40). The mapping causes the interconnect (10) to provide a channel by sending a task signal to the second peripheral (20) in response to a signal of the event from the first peripheral (18).