Patents by Inventor Jocel P. Gomez
Jocel P. Gomez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8067273Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is cooperatively structured with the lead with the flat surface, and an intermediate portion coupling the contact portion and the clip aligner structure.Type: GrantFiled: December 10, 2010Date of Patent: November 29, 2011Assignee: Fairchild Semiconductor CorporationInventor: Jocel P. Gomez
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Publication number: 20110095417Abstract: This document discusses, among other things, a semiconductor die having a first conductive bump coupled to a first electrical terminal at a first die surface of a semiconductor die and a dielectric substantially covering the first die surface and substantially surrounding the first conductive bump. A surface of the dielectric can include a recessed terminal area, and a second electrical terminal can be coupled to the first conductive bump in the recessed terminal area.Type: ApplicationFiled: October 28, 2009Publication date: April 28, 2011Applicant: Fairchild Semiconductor CorporationInventors: Jocel P. Gomez, Consuelo N. Tangpuz
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Publication number: 20110095410Abstract: This document discusses, among other things, a semiconductor connector including a conductive pad in a recessed pad area on a surface of a dielectric, the dielectric material configured to be activated to conductive plating deposition using laser ablation.Type: ApplicationFiled: October 28, 2009Publication date: April 28, 2011Applicant: Fairchild Semiconductor CorporationInventor: Jocel P. Gomez
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Publication number: 20110076807Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is cooperatively structured with the lead with the flat surface, and an intermediate portion coupling the contact portion and the clip aligner structure.Type: ApplicationFiled: December 10, 2010Publication date: March 31, 2011Inventor: Jocel P. Gomez
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Patent number: 7902657Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is cooperatively structured with the lead with the flat surface, and an intermediate portion coupling the contact portion and the clip aligner structure.Type: GrantFiled: August 28, 2007Date of Patent: March 8, 2011Assignee: Fairchild Semiconductor CorporationInventor: Jocel P. Gomez
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Patent number: 7824966Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure.Type: GrantFiled: August 19, 2009Date of Patent: November 2, 2010Assignee: Fairchild Semiconductor CorporationInventors: Maria Clemens Y. Quinones, Jocel P. Gomez
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Publication number: 20100267206Abstract: A semiconductor die package including at least two heat sinks. The semiconductor die package includes a first heat sink, a second heat sink coupled to the first heat sink, and a semiconductor die between the first heat sink and the second heat sink. The semiconductor die is electrically coupled to the first heat sink and the second heat sink. The semiconductor die may also be attached to a lead.Type: ApplicationFiled: May 3, 2010Publication date: October 21, 2010Inventor: Jocel P. Gomez
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Patent number: 7737548Abstract: A semiconductor die package including at least two heat sinks. The semiconductor die package includes a first heat sink, a second heat sink coupled to the first heat sink, and a semiconductor die between the first heat sink and the second heat sink. The semiconductor die is electrically coupled to the first heat sink and the second heat sink. The semiconductor die may also be attached to a lead.Type: GrantFiled: August 29, 2007Date of Patent: June 15, 2010Assignee: Fairchild Semiconductor CorporationInventor: Jocel P. Gomez
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Publication number: 20090311832Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure.Type: ApplicationFiled: August 19, 2009Publication date: December 17, 2009Inventors: Maria Clemens Y. QuiƱones, Jocel P. Gomez
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Publication number: 20090294985Abstract: Chip scale semiconductor packages and methods for making and using such semiconductor packages are described. The chip scale packages include multiple terminals that are each disposed on a die back surface that is located opposite to an active area of a semiconductor substrate in the package. The active area can be electrically connected to a plurality of terminals by using traces that may be electrically isolated from the die substrate. In some designs, the terminals can comprise a gate terminal that electrically connected with a gate region of the active area, a source terminal electrically connected with a source region of the active area, and a drain terminal may electrically connected with the die substrate. Other embodiments are also described.Type: ApplicationFiled: May 29, 2008Publication date: December 3, 2009Inventor: Jocel P. Gomez
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Patent number: 7626249Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure.Type: GrantFiled: January 10, 2008Date of Patent: December 1, 2009Assignee: Fairchild Semiconductor CorporationInventors: Maria Clemens Y. Quinones, Jocel P. Gomez
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Publication number: 20090194856Abstract: A semiconductor die package is disclosed. The semiconductor die package is suitable for mounting on a circuit substrate such as a circuit board. The semiconductor die package comprises a leadframe structure and a semiconductor die coupled to the leadframe structure. A plurality of first conductive structures is attached to the semiconductor die, and a plurality of second conductive structures is attached to the plurality of first conductive structures. The semiconductor die package also comprises a molding material that covers at least portions of plurality of first conductive structures, the leadframe structure, and the semiconductor die.Type: ApplicationFiled: February 6, 2008Publication date: August 6, 2009Inventor: Jocel P. Gomez
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Publication number: 20090179313Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure.Type: ApplicationFiled: January 10, 2008Publication date: July 16, 2009Inventors: Maria Clemens Quinones, Jocel P. Gomez
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Publication number: 20090127677Abstract: Semiconductor packages that contain leads with multiple terminals are described. The leads have a side terminal that can extend between a top terminal and a bottom terminal. The multiple terminals in the leads allow the semiconductor package to be connected to more than one external substrate and give the package multiple land pattern options. The semiconductor package can contain one or more dies that are connected to a lead frame in the package without the use of a clip. The back side of the die may be externally exposed from the package to help dissipate heat.Type: ApplicationFiled: November 21, 2007Publication date: May 21, 2009Inventor: Jocel P. Gomez
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Publication number: 20090127676Abstract: Back to back die assemblies used in semiconductor devices and methods for making such devices are described. The die assemblies are made by stacking two dies together so that the back of one die (that does not contain any active electronic components) is attached to the back of another die. At the same time, though, the dies are electrically isolated from each other. This configuration provides a device with a small package size and a small land pattern. As well, a minimum number of metal traces are used in the semiconductor devices, leading to a very low on-resistance (RDS) based on the size of the device footprint.Type: ApplicationFiled: November 16, 2007Publication date: May 21, 2009Inventor: Jocel P. Gomez
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Publication number: 20090057854Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is cooperatively structured with the lead with the flat surface, and an intermediate portion coupling the contact portion and the clip aligner structure.Type: ApplicationFiled: August 28, 2007Publication date: March 5, 2009Inventor: Jocel P. Gomez
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Publication number: 20090057878Abstract: A semiconductor die package including at least two heat sinks. The semiconductor die package includes a first heat sink, a second heat sink coupled to the first heat sink, and a semiconductor die between the first heat sink and the second heat sink. The semiconductor die is electrically coupled to the first heat sink and the second heat sink. The semiconductor die may also be attached to a lead.Type: ApplicationFiled: August 29, 2007Publication date: March 5, 2009Inventor: Jocel P. Gomez