Patents by Inventor Jocel P. Gomez

Jocel P. Gomez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8067273
    Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is cooperatively structured with the lead with the flat surface, and an intermediate portion coupling the contact portion and the clip aligner structure.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: November 29, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jocel P. Gomez
  • Publication number: 20110095417
    Abstract: This document discusses, among other things, a semiconductor die having a first conductive bump coupled to a first electrical terminal at a first die surface of a semiconductor die and a dielectric substantially covering the first die surface and substantially surrounding the first conductive bump. A surface of the dielectric can include a recessed terminal area, and a second electrical terminal can be coupled to the first conductive bump in the recessed terminal area.
    Type: Application
    Filed: October 28, 2009
    Publication date: April 28, 2011
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Jocel P. Gomez, Consuelo N. Tangpuz
  • Publication number: 20110095410
    Abstract: This document discusses, among other things, a semiconductor connector including a conductive pad in a recessed pad area on a surface of a dielectric, the dielectric material configured to be activated to conductive plating deposition using laser ablation.
    Type: Application
    Filed: October 28, 2009
    Publication date: April 28, 2011
    Applicant: Fairchild Semiconductor Corporation
    Inventor: Jocel P. Gomez
  • Publication number: 20110076807
    Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is cooperatively structured with the lead with the flat surface, and an intermediate portion coupling the contact portion and the clip aligner structure.
    Type: Application
    Filed: December 10, 2010
    Publication date: March 31, 2011
    Inventor: Jocel P. Gomez
  • Patent number: 7902657
    Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is cooperatively structured with the lead with the flat surface, and an intermediate portion coupling the contact portion and the clip aligner structure.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: March 8, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jocel P. Gomez
  • Patent number: 7824966
    Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: November 2, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Maria Clemens Y. Quinones, Jocel P. Gomez
  • Publication number: 20100267206
    Abstract: A semiconductor die package including at least two heat sinks. The semiconductor die package includes a first heat sink, a second heat sink coupled to the first heat sink, and a semiconductor die between the first heat sink and the second heat sink. The semiconductor die is electrically coupled to the first heat sink and the second heat sink. The semiconductor die may also be attached to a lead.
    Type: Application
    Filed: May 3, 2010
    Publication date: October 21, 2010
    Inventor: Jocel P. Gomez
  • Patent number: 7737548
    Abstract: A semiconductor die package including at least two heat sinks. The semiconductor die package includes a first heat sink, a second heat sink coupled to the first heat sink, and a semiconductor die between the first heat sink and the second heat sink. The semiconductor die is electrically coupled to the first heat sink and the second heat sink. The semiconductor die may also be attached to a lead.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: June 15, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jocel P. Gomez
  • Publication number: 20090311832
    Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure.
    Type: Application
    Filed: August 19, 2009
    Publication date: December 17, 2009
    Inventors: Maria Clemens Y. QuiƱones, Jocel P. Gomez
  • Publication number: 20090294985
    Abstract: Chip scale semiconductor packages and methods for making and using such semiconductor packages are described. The chip scale packages include multiple terminals that are each disposed on a die back surface that is located opposite to an active area of a semiconductor substrate in the package. The active area can be electrically connected to a plurality of terminals by using traces that may be electrically isolated from the die substrate. In some designs, the terminals can comprise a gate terminal that electrically connected with a gate region of the active area, a source terminal electrically connected with a source region of the active area, and a drain terminal may electrically connected with the die substrate. Other embodiments are also described.
    Type: Application
    Filed: May 29, 2008
    Publication date: December 3, 2009
    Inventor: Jocel P. Gomez
  • Patent number: 7626249
    Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: December 1, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Maria Clemens Y. Quinones, Jocel P. Gomez
  • Publication number: 20090194856
    Abstract: A semiconductor die package is disclosed. The semiconductor die package is suitable for mounting on a circuit substrate such as a circuit board. The semiconductor die package comprises a leadframe structure and a semiconductor die coupled to the leadframe structure. A plurality of first conductive structures is attached to the semiconductor die, and a plurality of second conductive structures is attached to the plurality of first conductive structures. The semiconductor die package also comprises a molding material that covers at least portions of plurality of first conductive structures, the leadframe structure, and the semiconductor die.
    Type: Application
    Filed: February 6, 2008
    Publication date: August 6, 2009
    Inventor: Jocel P. Gomez
  • Publication number: 20090179313
    Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure.
    Type: Application
    Filed: January 10, 2008
    Publication date: July 16, 2009
    Inventors: Maria Clemens Quinones, Jocel P. Gomez
  • Publication number: 20090127677
    Abstract: Semiconductor packages that contain leads with multiple terminals are described. The leads have a side terminal that can extend between a top terminal and a bottom terminal. The multiple terminals in the leads allow the semiconductor package to be connected to more than one external substrate and give the package multiple land pattern options. The semiconductor package can contain one or more dies that are connected to a lead frame in the package without the use of a clip. The back side of the die may be externally exposed from the package to help dissipate heat.
    Type: Application
    Filed: November 21, 2007
    Publication date: May 21, 2009
    Inventor: Jocel P. Gomez
  • Publication number: 20090127676
    Abstract: Back to back die assemblies used in semiconductor devices and methods for making such devices are described. The die assemblies are made by stacking two dies together so that the back of one die (that does not contain any active electronic components) is attached to the back of another die. At the same time, though, the dies are electrically isolated from each other. This configuration provides a device with a small package size and a small land pattern. As well, a minimum number of metal traces are used in the semiconductor devices, leading to a very low on-resistance (RDS) based on the size of the device footprint.
    Type: Application
    Filed: November 16, 2007
    Publication date: May 21, 2009
    Inventor: Jocel P. Gomez
  • Publication number: 20090057854
    Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is cooperatively structured with the lead with the flat surface, and an intermediate portion coupling the contact portion and the clip aligner structure.
    Type: Application
    Filed: August 28, 2007
    Publication date: March 5, 2009
    Inventor: Jocel P. Gomez
  • Publication number: 20090057878
    Abstract: A semiconductor die package including at least two heat sinks. The semiconductor die package includes a first heat sink, a second heat sink coupled to the first heat sink, and a semiconductor die between the first heat sink and the second heat sink. The semiconductor die is electrically coupled to the first heat sink and the second heat sink. The semiconductor die may also be attached to a lead.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 5, 2009
    Inventor: Jocel P. Gomez