Patents by Inventor Jochen Behrens

Jochen Behrens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250088449
    Abstract: Some embodiments provide a method for a data message processing device that includes multiple network interfaces associated with at least two different non-uniform memory access (NUMA) nodes. The method receives a data message at a first network interface associated with a particular one of the NUMA nodes. Based on processing of the data message, the method identifies multiple output options for the data message. Each of the output options has an equal forwarding cost and each output option is associated with a respective one of the NUMA nodes. The method selects an output option for the data message that is associated with the particular NUMA node to avoid cross-NUMA node processing of the data message.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 13, 2025
    Inventors: Xinhua Hong, Jochen Behrens, Yu Ying, Pankaj Gupta
  • Patent number: 11570011
    Abstract: Example methods and systems for multicast packet handling based on flow cache information are described. In one example, a network element may configure flow cache information associated with a multicast flow. The flow cache information may specify a set of actions that is configured based on a sequence of function calls. In response to detecting a multicast packet associated with the multicast flow, fast-path processing may be performed based on the flow cache information. This may include executing a replication action to generate a first packet replica and a second packet replica. First processing action(s) may be executed to process the first packet replica to generate and send a first output packet towards a first multicast destination. Second processing action(s) may be executed to process the second packet replica to generate and send a first output packet towards a second multicast destination.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: January 31, 2023
    Assignee: VMWARE, INC.
    Inventors: Dexiang Wang, Xinhua Hong, Yong Wang, Yu Ying, Jochen Behrens
  • Publication number: 20230020509
    Abstract: Described herein are systems, methods, and software to manage replay windows in multipath connections between gateways. In one implementation, a first gateway may receive a packet directed toward a second gateway and identify a path from a plurality of paths to the second gateway. Once identified, the first gateway may increment a sequence number associated with the path and encapsulate the packet with a unique identifier for the path in the header with the incremented sequence number. The first gateway the communicates the encapsulated packet to the second gateway.
    Type: Application
    Filed: October 4, 2021
    Publication date: January 19, 2023
    Inventors: AWAN KUMAR SHARMA, YONG WANG, SOURABH BHATTACHARYA, DEEPIKA KUNAL SOLANKI, SARTHAK RAY, JOCHEN BEHRENS
  • Patent number: 11552878
    Abstract: Described herein are systems, methods, and software to manage replay windows in multipath connections between gateways. In one implementation, a first gateway may receive a packet directed toward a second gateway and identify a path from a plurality of paths to the second gateway. Once identified, the first gateway may increment a sequence number associated with the path and encapsulate the packet with a unique identifier for the path in the header with the incremented sequence number. The first gateway the communicates the encapsulated packet to the second gateway.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: January 10, 2023
    Assignee: VMware, Inc.
    Inventors: Awan Kumar Sharma, Yong Wang, Sourabh Bhattacharya, Deepika Kunal Solanki, Sarthak Ray, Jochen Behrens
  • Patent number: 11509638
    Abstract: Example methods and computer systems for receive-side processing for encapsulated encrypted packets. One example may comprise: in response to receiving, over a tunnel, a first encapsulated encrypted packet that includes a first encrypted inner packet and a first outer header, generating a first decrypted inner packet by performing decryption and decapsulation; and based on content of the first decrypted inner packet, assigning the first decrypted inner packet to a first processing unit. The method may further comprise: in response to receiving, over the tunnel, a second encapsulated encrypted packet that includes a second encrypted inner packet and a second outer header, generating a second decrypted inner packet by performing decryption and decapsulation; and based on content of the second decrypted inner packet, assigning the second decrypted inner packet to a second processing unit, thereby distributing post-cryptography processing over multiple processing units.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: November 22, 2022
    Assignee: VMWARE, INC.
    Inventors: Yong Wang, Jochen Behrens
  • Publication number: 20220217006
    Abstract: Example methods and systems for multicast packet handling based on flow cache information are described. In one example, a network element may configure flow cache information associated with a multicast flow. The flow cache information may specify a set of actions that is configured based on a sequence of function calls. In response to detecting a multicast packet associated with the multicast flow, fast-path processing may be performed based on the flow cache information. This may include executing a replication action to generate a first packet replica and a second packet replica. First processing action(s) may be executed to process the first packet replica to generate and send a first output packet towards a first multicast destination. Second processing action(s) may be executed to process the second packet replica to generate and send a first output packet towards a second multicast destination.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 7, 2022
    Applicant: VMware, Inc.
    Inventors: Dexiang WANG, Xinhua HONG, Yong WANG, Yu YING, Jochen BEHRENS
  • Publication number: 20210185025
    Abstract: Example methods and computer systems for receive-side processing for encapsulated encrypted packets. One example may comprise: in response to receiving, over a tunnel, a first encapsulated encrypted packet that includes a first encrypted inner packet and a first outer header, generating a first decrypted inner packet by performing decryption and decapsulation; and based on content of the first decrypted inner packet, assigning the first decrypted inner packet to a first processing unit. The method may further comprise: in response to receiving, over the tunnel, a second encapsulated encrypted packet that includes a second encrypted inner packet and a second outer header, generating a second decrypted inner packet by performing decryption and decapsulation; and based on content of the second decrypted inner packet, assigning the second decrypted inner packet to a second processing unit, thereby distributing post-cryptography processing over multiple processing units.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 17, 2021
    Applicant: VMware, Inc.
    Inventors: Yong WANG, Jochen BEHRENS
  • Patent number: 9396159
    Abstract: A server interconnect system includes a first server node operable to send and receive messages and a second server nodes operable to send and receive messages. The system further comprises a first interface unit in communication with the first server node and a second interface unit in communication with the second server node. The first interface unit has a first set of message send registers and a first set of message receive registers. Similarly, the second interface unit has a second set of message send registers and a second set of message receive registers. The server interconnect system also includes a communication switch that receives and routes a message from the first or second server nodes when either of the first or second registers indicates that a valid message is ready to be sent. A method implemented by the server interconnect system is also provided.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: July 19, 2016
    Assignee: Oracle America, Inc.
    Inventors: Michael K. Wong, Rabin A. Sugumar, Stephen E. Phillips, Hugh Kurth, Suraj Sudhir, Jochen Behrens
  • Patent number: 8392824
    Abstract: A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), one or more hardware XML parser units, one or more cryptographic units and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or may be parsed in segments (e.g., as it is received). A parser unit parses a document or segment character by character, validates characters, assembles tokens from the document, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: March 5, 2013
    Assignee: Oracle America, Inc.
    Inventors: Jochen Behrens, Marcelino M. Dignum, Wayne F. Seltzer, William T. Zaumen, John P. Petry, Santiago M. Pericas-Geertsen, Biswadeep Nag
  • Publication number: 20100180195
    Abstract: A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), one or more hardware XML parser units, one or more cryptographic units and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or may be parsed in segments (e.g., as it is received). A parser unit parses a document or segment character by character, validates characters, assembles tokens from the document, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g.
    Type: Application
    Filed: March 24, 2010
    Publication date: July 15, 2010
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Jochen Behrens, Marcelino M. Dignum, Wayne F. Seltzer, William T. Zaumen, John P. Petry, Santiago M. Pericas-Geertsen, Biswadeep Nag
  • Patent number: 7716577
    Abstract: A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), one or more hardware XML parser units, one or more cryptographic units and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or may be parsed in segments (e.g., as it is received). A parser unit parses a document or segment character by character, validates characters, assembles tokens from the document, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: May 11, 2010
    Assignee: Oracle America, Inc.
    Inventors: Jochen Behrens, Marcelino M. Dignum, Wayne F. Seltzer, William T. Zaumen, John P. Petry, Santiago M. Pericas-Geertsen, Biswadeep Nag
  • Patent number: 7665015
    Abstract: A hardware unit for parsing an XML document includes embedded logic or circuitry for accessing the document, decoding it to change a character set, validating individual characters of the document, extracting tokens, maintaining a symbol table and generating binary token headers to describe the document's structure and convey the document's data to an application. Tokenization, the process of identifying tokens and generating token headers, may be controlled by a finite state machine that recognizes XML delimiters in the document's markup and activates state transitions based on the current state and the recognized delimiter. The parser unit may be implemented within a hardware XML accelerator that includes a processor, a DMA engine, a cryptographic engine, memory (e.g., for storing a document, maintaining a symbol table) and various interfaces (e.g., network, memory, bus).
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: February 16, 2010
    Assignee: Sun Microsystems, Inc.
    Inventors: Marcelino M. Dignum, Jochen Behrens, Wayne F. Seltzer, William T. Zaumen
  • Patent number: 7665016
    Abstract: A method and apparatus for performing virtualized parsing of an XML document. A document is divided into multiple segments, which may correspond to separate packets containing portions of the document, disk blocks, memory pages, etc. For each segment, a processor operating within an XML accelerator initiates parsing by identifying to a hardware parsing unit the document segment, a symbol table for the document and a location for storing state information regarding the parsing. Each segment is parsed in sequence, and the state information of the parsing is stored after each segment is completed, for retrieval when the next segment is to be parsed.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: February 16, 2010
    Assignee: Sun Microsystems, Inc.
    Inventors: Jochen Behrens, Marcelino M. Dignum, Wayne F. Seltzer, William T. Zaumen
  • Patent number: 7596745
    Abstract: A hardware finite state machine for facilitating the processing of an XML (Extensible Markup Language) document or other structured data stream. An accelerator is implemented in hardware to enable fast processing of a document (or a segment thereof). The accelerator includes a finite state machine that embodies a ternary CAM (Content-Addressable Memory) and associated RAM (Random Access Memory). Processing of the document is divided into multiple states, with each state transition defined by a markup delimiter that triggers the transition. The CAM is programmed with entries containing the processing states and, for each possible transition from that state, a pattern for matching delimiters that trigger the possible transitions. For a CAM entry matching the current processing state and a sequence of characters from the document, which may contain a delimiter, the associated RAM identifies the next state and any action to be taken (e.g., to shift the sequence of characters).
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: September 29, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Marcelino M. Dignum, Jochen Behrens, Wayne F. Seltzer
  • Publication number: 20090080439
    Abstract: A server interconnect system includes a first server node operable to send and receive messages and a second server nodes operable to send and receive messages. The system further comprises a first interface unit in communication with the first server node and a second interface unit in communication with the second server node. The first interface unit has a first set of message send registers and a first set of message receive registers. Similarly, the second interface unit has a second set of message send registers and a second set of message receive registers. The server interconnect system also includes a communication switch that receives and routes a message from the first or second server nodes when either of the first or second registers indicates that a valid message is ready to be sent. A method implemented by the server interconnect system is also provided.
    Type: Application
    Filed: September 25, 2007
    Publication date: March 26, 2009
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Michael K. Wong, Rabin A. Sugumar, Stephen E. Phillips, Hugh Kurth, Suraj Sudhir, Jochen Behrens
  • Publication number: 20090083392
    Abstract: A server interconnect system for sending data includes a first server node and a second server node. Each server node is operable to send and receive data. The interconnect system also includes a first and second interface unit. The first interface unit is in communication with the first server node and has one or more RDMA doorbell registers. Similarly, the second interface unit is in communication with the second server node and has one or more RDMA doorbell registers. The system also includes a communication switch that is operable to receive and route data from the first or second server nodes using a RDMA read and/or an RDMA write when either of the first or second RDMA doorbell registers indicates that data is ready to be sent or received.
    Type: Application
    Filed: September 25, 2007
    Publication date: March 26, 2009
    Applicant: Sun Microsystems, Inc.
    Inventors: Michael K. Wong, Rabin A. Sugumar, Stephen E. Phillips, Hugh Kurth, Suraj Sudhir, Jochen Behrens
  • Publication number: 20070113172
    Abstract: A method and apparatus for performing virtualized parsing of an XML document. A document is divided into multiple segments, which may correspond to separate packets containing portions of the document, disk blocks, memory pages, etc. For each segment, a processor operating within an XML accelerator initiates parsing by identifying to a hardware parsing unit the document segment, a symbol table for the document and a location for storing state information regarding the parsing. Each segment is parsed in sequence, and the state information of the parsing is stored after each segment is completed, for retrieval when the next segment is to be parsed.
    Type: Application
    Filed: November 14, 2005
    Publication date: May 17, 2007
    Inventors: Jochen Behrens, Marcelino Dignum, Wayne Seltzer, William Zaumen
  • Publication number: 20070113222
    Abstract: A hardware unit for parsing an XML document includes embedded logic or circuitry for accessing the document, decoding it to change a character set, validating individual characters of the document, extracting tokens, maintaining a symbol table and generating binary token headers to describe the document's structure and convey the document's data to an application. Tokenization, the process of identifying tokens and generating token headers, may be controlled by a finite state machine that recognizes XML delimiters in the document's markup and activates state transitions based on the current state and the recognized delimiter. The parser unit may be implemented within a hardware XML accelerator that includes a processor, a DMA engine, a cryptographic engine, memory (e.g., for storing a document, maintaining a symbol table) and various interfaces (e.g., network, memory, bus).
    Type: Application
    Filed: November 14, 2005
    Publication date: May 17, 2007
    Inventors: Marcelino Dignum, Jochen Behrens, Wayne Seltzer, William Zaumen
  • Publication number: 20070113170
    Abstract: A hardware finite state machine for facilitating the processing of an XML (Extensible Markup Language) document or other structured data stream. An accelerator is implemented in hardware to enable fast processing of a document (or a segment thereof). The accelerator includes a finite state machine that embodies a ternary CAM (Content-Addressable Memory) and associated RAM (Random Access Memory). Processing of the document is divided into multiple states, with each state transition defined by a markup delimiter that triggers the transition. The CAM is programmed with entries containing the processing states and, for each possible transition from that state, a pattern for matching delimiters that trigger the possible transitions. For a CAM entry matching the current processing state and a sequence of characters from the document, which may contain a delimiter, the associated RAM identifies the next state and any action to be taken (e.g., to shift the sequence of characters).
    Type: Application
    Filed: November 14, 2005
    Publication date: May 17, 2007
    Inventors: Marcelino Dignum, Jochen Behrens, Wayne Seltzer
  • Publication number: 20070113171
    Abstract: A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), one or more hardware XML parser units, one or more cryptographic units and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or may be parsed in segments (e.g., as it is received). A parser unit parses a document or segment character by character, validates characters, assembles tokens from the document, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g.
    Type: Application
    Filed: November 14, 2005
    Publication date: May 17, 2007
    Inventors: Jochen Behrens, Marcelino Dignum, Wayne Seltzer, William Zaumen, John Petry, Santiago Pericas-Geertsen, Biswadeep Nag