Patents by Inventor Jochen Hanebeck

Jochen Hanebeck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6635567
    Abstract: Alignment marks (overlay marks or alignment markers) are produced in a semiconductor structure with integrated circuits. Contact holes and alignment trenches are etched into an insulator layer and in each case open out at a first metal layer at their undersides. Metal is deposited into the alignment trenches and the contact holes. With a subsequent chemical mechanical polishing procedure, the metal areas are lowered in the region of the alignment trenches and form profiles for the alignment marks in a second metal layer, which is deposited on the insulator layer.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: October 21, 2003
    Assignee: Infineon Technologies AG
    Inventors: Eva Ebertseder, Matthias Lehr, Torsten Werneke, Jochen Hanebeck, Jürgen Pahlitzsch
  • Publication number: 20010019880
    Abstract: Alignment marks (overlay marks or alignment markers) are produced in a semiconductor structure with integrated circuits. Contact holes and alignment trenches are etched into an insulator layer and in each case open out at a first metal layer at their undersides. Metal is deposited into the alignment trenches and the contact holes. With a subsequent chemical mechanical polishing procedure, the metal areas are lowered in the region of the alignment trenches and form profiles for the alignment marks in a second metal layer, which is deposited on the insulator layer.
    Type: Application
    Filed: January 11, 2001
    Publication date: September 6, 2001
    Inventors: Eva Ebertseder, Matthias Lehr, Torsten Werneke, Jochen Hanebeck, Jurgen Pahlitzsch
  • Patent number: 5866485
    Abstract: A method in a plasma processing chamber for improving oxide-to-nitride selectivity while etching a borophosphosilicate glass (BPSG)-containing layer to create a self-aligned contact on a semiconductor substrate. The (BPSG)-containing layer is disposed on a SiN layer and into a via formed through the SiN layer. The method includes placing the substrate into the plasma processing chamber, and flowing an etchant source gas into the plasma processing chamber. The etchant source gas includes C.sub.4 F.sub.8 and an additive gas other than carbon monoxide (CO). The additive gas includes molecules having both oxygen atoms and carbon atoms in a 1:1 ratio. The method further includes exciting the etchant source gas with a radio frequency (RF) power source having a frequency of 13.56 MHz to strike a plasma from the etchant source gas, thereby etching at least partially through the BPSG-containing layer.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: February 2, 1999
    Assignee: Siemens Aktiengesellschaft
    Inventors: Markus M. Kirchhoff, Jochen Hanebeck